CY24272

Document Number: 001-42414 Rev. *A

Page 8 of 16

DC Operating Conditions

Parameter

Description

Condition

Min

Max

Unit

Supply Voltage for PLL

2.5 V ± 5%

2.375

2.625

V

Supply Voltage for Core

2.5 V ± 5%

2.375

2.625

V

Supply Voltage for Clock Buffers

2.5 V ± 5%

2.375

2.625

V

Input High Voltage, REFCLK/REFCLKB

0.6

0.95

V

Input Low Voltage, REFCLK/REFCLKB

–0.15

+0.15

V

Crossing Point Voltage, REFCLK/REFCLKB

200

550

mV

Difference in Crossing Point Voltage, REFCLK/REFCLKB

–

150

mV

Input Signal High Voltage at ID0, ID1, EN, and /BYPASS

1.4

2.625

V

Input Signal Low Voltage at ID0, ID1, EN, and /BYPASS

–0.15

0.8

V

Input Signal High Voltage at SCL and SDA[7]

1.4

3.465

V

Input Signal Low Voltage at SCL and SDA

–0.15

0.8

V

Input Threshold Voltage for single-ended REFCLK

0.35

V

Input Signal High Voltage for single-ended REFCLK

2.625

V

Input Signal Low Voltage for single-ended REFCLK

–0.15

V

Ambient Operating Temperature

0

70

°C

Notes

7. This range of SCL and SDA input high voltage enables the CY24272 for use with 3.3 V, 2.5 V, or 1.8 V SMBus voltages.

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