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CY2305CSXA-1H Datasheet(PDF) 8 Page - Cypress Semiconductor |
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CY2305CSXA-1H Datasheet(HTML) 8 Page - Cypress Semiconductor |
8 / 17 page CY2305C CY2309C Document Number: 38-07672 Rev. *K Page 8 of 17 Switching Characteristics for CY2305CSXC-XX and CY2309CSXC-XX Switching characteristics table for CY2305CSXC-1H and CY2309CSXC-1H commercial temperature devices. All parameters are specified with loaded outputs. Parameter Name Description Min Typ Max Unit t1 Output frequency 30-pF load 10-pF load 10 10 –100 133.33 MHz MHz tDC Output duty cycle[11] = t2 t1 Measured at 1.4 V, Fout > 50 MHz 40 50 60 % Measured at 1.4 V, Fout 50 MHz 45 50 55 % t3 Rise time[11] Measured between 0.8 V and 2.0 V – – 1.5 ns t4 Fall time[11] Measured between 0.8 V and 2.0 V – – 1.5 ns t5 Output-to-output skew[11] All outputs equally loaded – – 200 ps t6A Delay, REF rising edge to CLKOUT rising edge[11] Measured at VDD/2 – 0 ±350 ps t6B Delay, REF rising edge to CLKOUT rising edge[11] Measured at VDD/2. Measured in PLL Bypass mode, CY2309C device only. 15 8.7 ns t7 Device-to-device skew[11] Measured at VDD/2 on the CLKOUT pins of devices –0 700 ps t8 Output slew rate[11] Measured between 0.8 V and 2.0 V using Test circuit #2 1– – V/ns tJ Cycle-to-cycle jitter, peak[11] Measured at 66.67 MHz, loaded outputs – – 175 ps tLOCK PLL lock time[11] Stable power supply, valid clock presented on REF pin –– 1.0 ms Note 11. Parameter is guaranteed by design and characterization. Not 100% tested in production. Switching Characteristics for CY2305CSXI-XX, CY2305CSXA-XX and CY2309CSXI-XX Switching characteristics table for CY2305CSXI-1, CY2305CSXA-1, and CY2309CSXI-1 industrial temperature devices. All parameters are specified with loaded outputs. Parameter Name Test Conditions Min Typ Max Unit t1 Output frequency 30 pF load 10 pF load 10 10 –100 133.33 MHz MHz tDC Output duty cycle[11] = t2 t1 Measured at 1.4 V, Fout > 50 MHz 40 50 60 % Measured at 1.4 V, Fout <= 50 MHz 45 50 55 % t3 Rise time[11] Measured between 0.8 V and 2.0 V – – 2.25 ns t4 Fall time[11] Measured between 0.8 V and 2.0 V – – 2.25 ns t5 Output-to-output skew[11] All outputs equally loaded – – 200 ps t6A Delay, REF rising edge to CLKOUT rising edge[11] Measured at VDD/2 – 0 ±350 ps t6B Delay, REF rising edge to CLKOUT rising edge[11] Measured at VDD/2. Measured in PLL Bypass mode, CY2309C device only. 15 8.7 ns t7 Device-to-device skew[11] Measured at VDD/2 on the CLKOUT pins of devices –0 700 ps tJ Cycle-to-cycle jitter, peak[11] Measured at 66.67 MHz, loaded outputs – 50 175 ps tLOCK PLL lock time[11] Stable power supply, valid clock presented on REF pin –– 1.0 ms [+] Feedback |
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