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CY2305SC-1T Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CY2305SC-1T Datasheet(HTML) 5 Page - Cypress Semiconductor |
5 / 19 page CY2305, CY2309 Document Number : 38-07140 Rev. *M Page 5 of 19 Absolute Maximum Conditions Supply voltage to ground potential ...............–0.5 V to +7.0 V DC input voltage (Except REF) .......... –0.5 V to VDD + 0.5 V DC input voltage REF ........................................–0.5 V to 7 V Storage temperature .................................. –65°C to +150°C Junction temperature.................................................. 150°C Static discharge voltage (per MIL-STD-883, Method 3015) .......................... > 2,000 V Operating Conditions for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices Parameter Description Min Max Unit VDD Supply voltage 3.0 3.6 V TA Operating temperature (ambient temperature) 0 70 °C CL Load capacitance, below 100 MHz – 30 pF CL Load capacitance, from 100 MHz to 133 MHz – 10 pF CIN Input capacitance – 7 pF tPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms Electrical Characteristics for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices Parameter Description Test Conditions Min Max Unit VIL Input LOW voltage[6] –0.8 V VIH Input HIGH voltage[6] 2.0 – V IIL Input LOW current VIN = 0 V – 50.0 μA IIH Input HIGH current VIN = VDD – 100.0 μA VOL Output LOW voltage[7] IOL = 8 mA (–1) IOH = 12 mA (–1H) –0.4 V VOH Output HIGH voltage[7] IOH = –8 mA (–1) IOL = –12 mA (–1H) 2.4 – V IDD (PD mode) Power-down supply current REF = 0 MHz – 12.0 μA IDD Supply current Unloaded outputs at 66.67 MHz, SEL inputs at VSS –32.0 mA Switching Characteristics for CY2305SC-1 and CY2309SC-1 Commercial Temperature Devices Parameter[9] Name Test Conditions Min Typ. Max Unit t1 Output frequency 30-pF load 10-pF load 10 10 –100 133.33 MHz MHz tDC Duty cycle[7] = t2 ÷ t1 Measured at 1.4 V, Fout = 66.67 MHz 40.0 50.0 60.0 % t3 Rise time[7] Measured between 0.8 V and 2.0 V – – 2.50 ns t4 Fall time[7] Measured between 0.8 V and 2.0 V – – 2.50 ns t5 Output-to-output skew[7] All outputs equally loaded – 85 250 ps t6A Delay, REF rising edge to CLKOUT rising edge[7] Measured at VDD/2 – 0 ±350 ps Notes 6. REF input has a threshold voltage of VDD/2. 7. Parameter is guaranteed by design and characterization. Not 100% tested in production. [+] Feedback |
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