PRELIMINARY

CY14C101J

CY14B101J, CY14E101J

Document #: 001-54050 Rev. *D

Page 5 of 32

Data Validity

The data on the SDA line must be stable during the HIGH period

of the clock. The state of the data line can only change when the

clock on the SCL line is LOW for the data to be valid. There are

only two conditions under which the SDA line may change state

with SCL line held HIGH, that is, START and STOP condition.

The START and STOP conditions are generated by the master

to signal the beginning and end of a communication sequence

START Condition (S)

A HIGH to LOW transition on the SDA line while SCL is HIGH

with the master generating a START condition.

STOP Condition (P)

A LOW to HIGH transition on the SDA line while SCL is HIGH

indicates a STOP condition. This condition indicates the end of

the ongoing transaction.

START and STOP conditions are always generated by the

master. The bus is considered to be busy after the START

condition. The bus is considered to be free again after the STOP

condition.

Repeated START (Sr)

If an Repeated START condition is generated instead of a Stop

condition the bus continues to be busy. The ongoing transaction

send a slave ID for communication to restart.

Byte Format

ACK signal by the receiver.

An operation continues till a NACK is sent by the receiver or STOP or Repeated START condition is generated by the master The

SDA line must remain stable when the clock (SCL) is HIGH except for a START or STOP condition.

Figure 4. START and STOP Conditions

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SDA

SCL

P

STOP Condition

SDA

SCL

S

START Condition

handbook, full pagewidth

Sr

or

P

SDA

Sr

P

SCL

STOP or

Repeated START

condition

S

or

Sr

START or

Repeated START

condition

1

2

3 - 8

9

ACK

9

ACK

78

12

MSB

Acknowledgement

signal from slave

Byte complete,

interrupt within slave

Clock line held LOW while

interrupts are serviced

Acknowledgement

signal from receiver

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