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CY14B101J1-SXI Datasheet(PDF) 6 Page - Cypress Semiconductor |
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CY14B101J1-SXI Datasheet(HTML) 6 Page - Cypress Semiconductor |
6 / 32 page PRELIMINARY CY14C101J CY14B101J, CY14E101J Document #: 001-54050 Rev. *D Page 6 of 32 Acknowledge/No-acknowledge After transmitting one byte of data or address, the transmitter releases the SDA line. The receiver pulls the SDA line LOW to acknowledge the receipt of the byte. Every byte of data trans- ferred on the I2C bus needs to be responded with an ACK signal by the receiver to continue the operation. Failing to do so is considered as a NACK state. NACK is the state where receiver does not acknowledge the receipt of data and the operation is aborted. NACK can be generated by master during a READ operation in following cases: ■ The master did not receive valid data due to noise ■ The master generates a NACK to abort the READ sequence. After a NACK is issued by the master, nvSRAM slave releases control of the SDA pin and the master is free to generate a Repeated START or STOP condition. NACK can be generated by nvSRAM slave during a WRITE operation in following cases: ■ nvSRAM did not receive valid data due to noise. ■ The master tries to access write protected locations on the nvSRAM. Master must restart the communication by generating a STOP or Repeated START condition. High-Speed Mode (Hs-mode) In Hs-mode, nvSRAM can transfer data at bit rates of up to 3.4 bit/s. A master code (0000 1XXXb) must be issued to place the device into high speed mode. This enables master slave communication for speed upto 3.4 MHz. A stop condition exits Hs-mode. Serial Data Format in Hs-mode Serial data transfer format in Hs-mode meets the standard-mode I2C-bus specification. Hs-mode can only commence after the following conditions (all of which are in F/S-modes): 1. START condition (S) 2. 8-bit master code (0000 1XXXb) 3. No-acknowledge bit (A) Single and multiple-byte reads and writes are supported. After the device enters into Hs-mode, data transfer continues in Hs-mode until stop condition is sent by master device. The slave switches back to F/S-mode after a STOP condition (P). To continue data transfer in Hs-mode, the master sends Repeated START (Sr). See Figure 13 on page 11 and Figure 16 on page 12 for Hs-mode timings for read and write operation. Figure 6. Acknowledge on the I2C Bus handbook, full pagewidth S START condition 9 8 2 1 clock pulse for acknowledgement not acknowledge (A) acknowledge (A) DATA OUTPUT BY MASTER DATA OUTPUT BY SLAVE SCL FROM MASTER Figure 7. Data transfer format in Hs-mode handbook, full pagewidth F/S-mode Hs-mode F/S-mode AA / A A DATA n (bytes +ack.) W / R S MASTER CODE Sr SLAVE ADD. Hs-mode continues Sr SLAVE ADD. P [+] Feedback |
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