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CY14E101I-SFXI Datasheet(PDF) 7 Page - Cypress Semiconductor |
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CY14E101I-SFXI Datasheet(HTML) 7 Page - Cypress Semiconductor |
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7 / 42 page  PRELIMINARY CY14C101I CY14B101I, CY14E101I Document #: 001-54391 Rev. *C Page 7 of 42 High-Speed Mode (Hs-mode) In Hs-mode, nvSRAM can transfer data at bit rates of up to 3.4 Mbit/s. A master code (0000 1XXXb) must be issued to place the device in high-speed mode. This enables master/slave communication for speeds up to 3.4 MHz. A stop condition will exit Hs-mode. Serial Data Format in Hs-mode Serial data transfer format in Hs-mode meets the standard-mode I2C-bus specification. Hs-mode can only commence after the following conditions (all of which are in F/S-modes): 1. START condition (S) 2. 8-bit master code (0000 1XXXb) 3. No-acknowledge bit (A) Single and multiple-byte reads and writes are supported. After the device enters Hs-mode, data transfer continues in Hs-mode until stop condition is sent by master device. The slave switches back to F/S-mode after a STOP condition (P). To continue data transfer in Hs-mode, the master sends Repeated START (Sr). See Figure 13 on page 12 and Figure 16 on page 13 for HS-mode timings for read and write operation. Slave Device Address Every slave device on an I2C bus has a device select address. The first byte after START condition contains the slave device address with which the master intends to communicate. The seven MSBs are the device address and the LSB (R/W bit) is used for indicating Read or Write operation. The CY14X101I reserves three sets of upper 4 MSBs [7:4] in the slave device address field for accessing the Memory, RTC Registers, and Control Registers. The accessing mechanism is described in the following section. The nvSRAM product provides three different functionalities: Memory, RTC Registers and Control Registers functions (such as serial number and product ID). The three functions of the device are accessed through different slave device addresses. The first four most significant bits [7:4] in the device address register are used to select between the nvSRAM functions. Figure 6. Data Transfer Format in Hs-mode handbook, full pagewidth F/S-mode Hs-mode F/S-mode AA / A A DATA n (bytes +ack.) W / R S MASTER CODE Sr SLAVE ADD. Hs-mode continues Sr SLAVE ADD. P Table 2. Slave Device Addressing Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 nvSRAM Function Select CY14X101I Slave Devices 1 0 1 0 Device select ID A16 R/W Selects Memory Memory, 128K x 8 1 1 0 1 Device select ID X R/W Selects RTC Registers RTC Registers, 16 x 8 0 0 1 1 Device select ID X R/W Selects Control Registers Control Registers - Memory Control Register, 1 × 8 - Serial Number, 8 × 8 - Device ID, 4 × 8 - Command Register, 1 × 8 [+] Feedback |
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