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CY14B256KA-SP45XI Datasheet(PDF) 7 Page - Cypress Semiconductor |
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CY14B256KA-SP45XI Datasheet(HTML) 7 Page - Cypress Semiconductor |
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7 / 27 page  CY14B256KA Document #: 001-55720 Rev. *C Page 7 of 27 Data Protection The CY14B256KA protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC is less than VSWITCH. If the CY14B256KA is in a write mode (both CE and WE are LOW) at power-up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after tLZHSB (HSB to output active). This protects against inadvertent writes during power-up or brown out conditions. Noise Considerations Refer to CY application note AN1064. Real Time Clock Operation nvTIME Operation The CY14B256KA offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. Internal double buffering of the clock and timer information registers prevents accessing transitional internal clock data during a read or write operation. Double buffering also circumvents disrupting normal timing counts or the clock accuracy of the internal clock when accessing clock data. Clock and alarm registers store data in BCD format. RTC functionality is described in the following sections. The RTC register addresses for CY14B256KA range from 0x7FF0 to 0x7FFF. Refer to Table 3 on page 11 and Table 4 on page 12 for a detailed Register Map description. Clock Operations The clock registers maintain time up to 9,999 years in one second increments. The time can be set to any calendar time and the clock automatically keeps track of days of the week and month, leap years, and century transitions. There are eight registers dedicated to the clock functions, which are used to set time with a write cycle and to read time during a read cycle. These registers contain the time of day in BCD format. Bits defined as ‘0’ are currently not used and are reserved for future use by Cypress. Reading the Clock The double buffered RTC register structure reduces the chance of reading incorrect data from the clock. Stop internal updates to the CY14B256KA time keeping registers before reading clock data, to prevent reading of data in transition. Stopping the register updates does not affect clock accuracy. The updating process is stopped by writing a ‘1’ to the read bit ‘R’ (in the flags register at 0x7FF0), and does not restart until a ‘0’ is written to the read bit. The RTC registers are then read while the internal clock continues to run. After a ‘0’ is written to the read bit (‘R’), all RTC registers are simultaneously updated within 20 ms. Setting the Clock Setting the write bit ‘W’ (in the flags register at 0x7FF0) to a ‘1’ stops updates to the time keeping registers and enables the time to be set. The correct day, date, and time is then written into the registers and must be in 24-hour BCD format. The time written is referred to as the “Base Time”. This value is stored in nonvol- atile registers and used in the calculation of the current time. Resetting the write bit to ‘0’ transfers the values of timekeeping registers to the actual clock counters, after which the clock resumes normal operation. If the time written to the timekeeping registers is not in the correct BCD format, each invalid nibble of the RTC registers continue counting to 0xF before rolling over to 0x0 after which RTC resumes normal operation. Note After ‘W’ bit is set to ‘0’, values written into the timekeeping, alarm, calibration, and interrupt registers are transferred to the RTC time keeping counters in tRTCp time. These counter values must be saved to nonvolatile memory either by initiating a Software/Hardware STORE or AutoStore operation. While working in AutoStore disabled mode, perform a STORE operation after tRTCp time while writing into the RTC registers for the modifications to be correctly recorded. Backup Power The RTC in the CY14B256KA is intended for permanently powered operation. The VRTCcap or VRTCbat pin is connected depending on whether a capacitor or battery is chosen for the application. When the primary power, VCC, fails and drops below VSWITCH the device switches to the backup power supply. The clock oscillator uses very little current, which maximizes the backup time available from the backup source. Regardless of the clock operation with the primary source removed, the data stored in the nvSRAM is secure, having been stored in the nonvolatile elements when power was lost. During backup operation, the CY14B256KA consumes 0.35 microamps (Typical) at room temperature. The user must choose capacitor or battery values according to the application. Backup time values based on maximum current specifications are shown in the following table. Nominal backup times are approximately two times longer. Using a capacitor has the obvious advantage of recharging the backup source each time the system is powered up. If a battery is used, a 3 V lithium is recommended and the CY14B256KA sources current only from the battery when the primary power is removed. However, the battery is not recharged at any time by the CY14B256KA. The battery capacity must be chosen for total anticipated cumulative down time required over the life of the system. Table 2. RTC Backup Time Capacitor Value Backup Time 0.1 F 72 hours 0.47 F 14 days 1.0 F 30 days [+] Feedback |
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