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CY8C5386AXI-001 Datasheet(PDF) 10 Page - Cypress Semiconductor |
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CY8C5386AXI-001 Datasheet(HTML) 10 Page - Cypress Semiconductor |
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10 / 102 page  PRELIMINARY PSoC® 5: CY8C53 Family Datasheet Document Number: 001-55035 Rev. *G Page 10 of 102 VCCA. Output of analog core regulator and input to analog core. Requires a 1 µF capacitor to VSSA. Regulator output not for external use. VCCD. Output of digital core regulator and input to digital core. The two VCCD pins must be shorted together, with the trace between them as short as possible, and a 1 µF capacitor to VSSD; see Power System on page 23. Regulator output not for external use. VDDA. Supply for all analog peripherals and analog core regulator. VDDA must be the highest voltage present on the device. All other supply pins must be less than or equal to VDDA. VDDD. Supply for all digital peripherals and digital core regulator. VDDD must be less than or equal to VDDA. VSSA. Ground for all analog peripherals. VSSB. Ground connection for boost pump. VSSD. Ground for all digital logic and I/O pins. VDDIO0, VDDIO1, VDDIO2, VDDIO3. Supply for I/O pins. Each VDDIO must be tied to a valid operating voltage (1.71 V to 5.5 V), and must be less than or equal to VDDA. If the I/O pins associated with Vddio0, Vddio2 or Vddio3 are not used then that VDDIO should be tied to ground (VSSD or VSSA). XRES (and configurable XRES). External reset pin. Active low with internal pullup. In 48-pin SSOP parts, P1[2] is configured as XRES. In all other parts the pin is configured as a GPIO. 4. CPU 4.1 ARM Cortex-M3 CPU The CY8C53 family of devices has an ARM Cortex-M3 CPU core. The Cortex-M3 is a low power 32-bit three-stage pipelined Harvard architecture CPU that delivers 1.25 DMIPS/MHz. It is intended for deeply embedded applications that require fast interrupt handling features. Figure 4-1. ARM Cortex-M3 Block Diagram Nested Vectored Interrupt Controller (NVIC) Debug Block (Serial and JTAG) Embedded Trace Module (ETM) Trace Port Interface Unit (TPIU) Interrupt Inputs JTAG/SWD Trace Pins: 5 for TRACEPORT or 1 for SWV mode Cortex M3 CPU Core I- Bus S-Bus D-Bus 256 KB ECC Flash Cache 32 KB SRAM DMA AHB Bridge & Bus Matrix PHUB GPIO & EMIF Prog. Digital Prog. Analog Special Functions Peripherals AHB Spokes AHB AHB AHB Bus Matrix Cortex M3 Wrapper C-Bus Data Watchpoint and Trace (DWT) Instrumentation Trace Module (ITM) Flash Patch and Breakpoint (FPB) Bus Matrix 32 KB SRAM Bus Matrix [+] Feedback |
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Similar Description - CY8C5386AXI-001 |
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