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CY8C5385PVI-080 Datasheet(PDF) 3 Page - Cypress Semiconductor |
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CY8C5385PVI-080 Datasheet(HTML) 3 Page - Cypress Semiconductor |
3 / 102 page PRELIMINARY PSoC® 5: CY8C53 Family Datasheet Document Number: 001-55035 Rev. *G Page 3 of 102 1. Architectural Overview Introducing the CY8C53 family of ultra low-power, flash Programmable System-on-Chip (PSoC®) devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C53 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables a high level of integration in a wide variety of consumer, industrial, and medical applications. Figure 1-1. Simplified Block Diagram Analog System LCD Direct Drive CapSense Temperature Sensor 2x Opamp + - ADC 2x DAC 2 x SC/ CT Blocks (TIA, PGA, Mixer etc) 4 x CMP + - System Wide Resources Program Debug & Trace Boundary Scan Program & Debug 8051or Cortex M3 CPU Interrupt Controller PHUB DMA Cache Controller SRAM FLASH EEPROM EMIF CPU System Memory System System Bus Digital Interconnect Analog Interconnect 0. 5 to5.5V ( Optional) 4 33 MHz ( Optional) Xtal Osc 32.768 KHz ( Optional) RTC Timer IMO WDT and Wake ILO Clocking System 1.8 V LDO SMP POR and LVD Sleep Power Power Management System USB PHY 3 per Opamp SAR ADC CAN 2.0 I2C Master/ Slave Universal Digital Block Array (24 x UDB) 4 x Timer Counter PWM FS USB 2.0 Digital System UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UART Logic 12- Bit PWM I2C Slave 8- Bit SPI 12- Bit SPI Logic 8- Bit Timer 16- Bit PRS UDB 8- Bit Timer Quadrature Decoder 16- Bit PWM UDB UDB UDB UDB UDB UDB UDB UDB 22 to [+] Feedback |
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