CY7C14101KV18, CY7C14251KV18

CY7C14121KV18, CY7C14141KV18

Document Number: 001-56733 Rev. *E

Page 8 of 31

CQ

Echo Clock

CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock

for output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing for

the echo clocks is shown in Switching Characteristics on page 25.

CQ

Echo Clock

CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock

for output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing for

the echo clocks is shown in the Switching Characteristics on page 25.

ZQ

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

impedance mode. This pin cannot be connected directly to GND or left unconnected.

DOFF

Input

PLL Turn Off

 Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing

in the operation with the PLL turned off differs from those listed in this data sheet. For normal operation,

connect this pin to a pull up through a 10 K

 or less pull up resistor. The device behaves in QDR I mode

when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz

with QDR I timing.

TDO

Output

TDO for JTAG.

TCK

Input

TCK Pin for JTAG.

TDI

Input

TDI Pin for JTAG.

TMS

Input

TMS Pin for JTAG.

NC

N/A

Not Connected to the Die. Can be tied to any voltage level.

NC/144M

Input

Not Connected to the Die. Can be tied to any voltage level.

NC/288M

Input

Not Connected to the Die. Can be tied to any voltage level.

Input-

Reference

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC

measurement points.

Power Supply Power Supply Inputs to the Core of the Device.

Ground

Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

Pin Name

I/O

Pin Description

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