CY7C12611KV18, CY7C12761KV18

CY7C12631KV18, CY7C12651KV18

Document Number: 001-53193 Rev. *D

Page 7 of 30

Table 2. Pin Definitions

Pin Name

I/O

Pin Description

Input-

synchronous

Data input signals. Sampled on the rising edge of K and K clocks when valid write operations are active.

CY7C12611KV18

CY7C12761KV18

CY7C12631KV18

CY7C12651KV18

WPS

Input-

synchronous

Write port select

 Active LOW. Sampled on the rising edge of the K clock. When asserted active, a

Input-

synchronous

Nibble write select 0, 1

 Active LOW (CY7C12611KV18 Only). Sampled on the rising edge of the K

and K clocks when write operations are active. Used to select which nibble is written into the device

All the nibble write selects are sampled on the same edge as the data. Deselecting a Nibble Write Select

ignores the corresponding nibble of data and it is not written into the device.

Input-

synchronous

Byte write select 0, 1, 2 and 3

 Active LOW. Sampled on the rising edge of the K and K clocks when

write operations are active. Used to select which byte is written into the device during the current portion

of the write operations. Bytes not written remain unaltered.

CY7C12761KV18

CY7C12631KV18

CY7C12651KV18

All the byte write selects are sampled on the same edge as the data. Deselecting a Byte Write Select

ignores the corresponding byte of data and it is not written into the device.

A

Input-

synchronous

Address inputs. Sampled on the rising edge of the K clock during active read and write operations. These

address inputs are multiplexed for both read and write operations. Internally, the device is organized as

4M x 8 (4 arrays each of 1M x 8) for CY7C12611KV18, 4 M x 9 (4 arrays each of 1 M x 9) for

CY7C12761KV18, 2 M x 18 (4 arrays each of 512K x 18) for CY7C12631KV18, and 1 M x 36 (4 arrays

each of 256K x 36) for CY7C12651KV18. Therefore, only 20 address inputs are needed to access the

entire memory array of CY7C12611KV18 and CY7C12761KV18, 19 address inputs for CY7C12631KV18

and 18 address inputs for CY7C12651KV18. These inputs are ignored when the appropriate port is

deselected.

Outputs-

synchronous

Data output signals. These pins drive out the requested data when the read operation is active. Valid

data is driven out on the rising edge of the K and K clocks during read operations. On deselecting the

CY7C12611KV18

CY7C12761KV18

CY7C12631KV18

CY7C12651KV18

RPS

Input-

synchronous

Read port select

 Active LOW. Sampled on the rising edge of positive input clock (K). When active, a

read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is

allowed to complete and the output drivers are automatically tristated following the next rising edge of the

K clock. Each read access consists of a burst of four sequential transfers.

QVLD

Valid output

indicator

Valid output indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.

K

Input clock

Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device and

K

Input clock

Negative input clock input. K is used to capture synchronous inputs being presented to the device and

CQ

Echo clock

Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock

(K) of the QDR II+. The timings for the echo clocks are shown in the Switching Characteristics on page 24.

CQ

Echo clock

Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock

(K) of the QDR II+.The timings for the echo clocks are shown in the Switching Characteristics on page 24.

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