Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

CY7C1380F Datasheet(PDF) 8 Page - Cypress Semiconductor

Part # CY7C1380F
Description  18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM
Download  33 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1380F Datasheet(HTML) 8 Page - Cypress Semiconductor

Back Button CY7C1380F Datasheet HTML 4Page - Cypress Semiconductor CY7C1380F Datasheet HTML 5Page - Cypress Semiconductor CY7C1380F Datasheet HTML 6Page - Cypress Semiconductor CY7C1380F Datasheet HTML 7Page - Cypress Semiconductor CY7C1380F Datasheet HTML 8Page - Cypress Semiconductor CY7C1380F Datasheet HTML 9Page - Cypress Semiconductor CY7C1380F Datasheet HTML 10Page - Cypress Semiconductor CY7C1380F Datasheet HTML 11Page - Cypress Semiconductor CY7C1380F Datasheet HTML 12Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 33 page
background image
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Document Number: 38-05543 Rev. *I
Page 8 of 33
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry.
MODE
Input-Static
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence. This is a strap pin and must remain static during
device operation. Mode pin has an internal pull up.
TDO
JTAG serial
output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
feature is not being utilized, this pin must be disconnected. This pin is not available on TQFP
packages.
TDI
JTAG serial
input
Synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on
TQFP packages.
TMS
JTAG serial
input
Synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on
TQFP packages.
TCK
JTAG-
Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be
connected to VSS. This pin is not available on TQFP packages.
NC
No Connects. 36M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not
internally connected to the die.
Table 1. Pin Definitions (continued)
[+] Feedback


Similar Part No. - CY7C1380F

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1380F CYPRESS-CY7C1380F Datasheet
1Mb / 30P
   18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1380F CYPRESS-CY7C1380F Datasheet
1Mb / 37P
   18-Mbit (512 K x 36/1 M x 18) Pipelined SRAM
CY7C1380F-167BGC CYPRESS-CY7C1380F-167BGC Datasheet
1Mb / 30P
   18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1380F-167BGI CYPRESS-CY7C1380F-167BGI Datasheet
1Mb / 30P
   18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1380F-167BGXC CYPRESS-CY7C1380F-167BGXC Datasheet
1Mb / 30P
   18-Mbit (512K x 36/1M x 18) Pipelined SRAM
More results

Similar Description - CY7C1380F

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1380DV33 CYPRESS-CY7C1380DV33 Datasheet
1Mb / 33P
   18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM
CY7C1380S CYPRESS-CY7C1380S Datasheet
1Mb / 31P
   18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM
CY7C1386D CYPRESS-CY7C1386D_12 Datasheet
687Kb / 34P
   18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined DCD Sync SRAM
CY7C1370DV25 CYPRESS-CY7C1370DV25_12 Datasheet
774Kb / 30P
   18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM with NoBL??Architecture
CY7C1372D CYPRESS-CY7C1372D_12 Datasheet
968Kb / 31P
   18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM with NoBL??Architecture
CY7C1360C CYPRESS-CY7C1360C_12 Datasheet
1Mb / 37P
   9-Mbit (256 K 횞 36/512 K 횞 18) Pipelined SRAM
CY7C1381D CYPRESS-CY7C1381D_11 Datasheet
1Mb / 34P
   18 Mbit (512 K 횞 36/1 M 횞 18) Flow Through SRAM
CY7C1386S CYPRESS-CY7C1386S Datasheet
727Kb / 22P
   18-Mbit (512 K 횞 36) Pipelined DCD Sync SRAM
CY7C1384D CYPRESS-CY7C1384D Datasheet
709Kb / 20P
   18-Mbit (512 K 횞 32) Pipelined SRAM
CY7C1366C CYPRESS-CY7C1366C_12 Datasheet
984Kb / 32P
   9-Mbit (256 K 횞 36/512 K 횞 18) Pipelined DCD Sync SRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com