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PPC5643LFF0MMM1 Datasheet(PDF) 8 Page - Freescale Semiconductor, Inc

Part # PPC5643LFF0MMM1
Description  High-performance e200z4d dual core
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

PPC5643LFF0MMM1 Datasheet(HTML) 8 Page - Freescale Semiconductor, Inc

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MPC5643L Microcontroller Data Sheet, Rev. 6
Preliminary—Subject to Change Without Notice
Introduction
Freescale Semiconductor
8
Each DMA task can optionally generate an interrupt at completion and retirement of the task
Signal to indicate closure of last minor loop
Transfer control descriptors mapped inside the SRAM
The eDMA controller is replicated for each processing channel.
1.6.5
On-chip flash memory with ECC
This device includes programmable, non-volatile flash memory. The non-volatile memory (NVM) can be used for instruction
storage or data storage, or both. The flash memory module interfaces with the system bus through a dedicated flash memory
array controller. It supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory.
The module contains four 128-bit prefetch buffers. Prefetch buffer hits allow no-wait responses. Buffer misses incur a 3 wait
state response at 120 MHz.
The flash memory module provides the following features
1 MB of flash memory in unique multi-partitioned hard macro
Sectorization: 16 KB + 2 × 48 KB + 16 KB + 2 × 64 KB + 2 × 128 KB + 2 × 256 KB
EEPROM emulation (in software) within same module but on different partition
16 KB test sector and 16 KB shadow sector for test, censorship device and user option bits
Wait states:
— 3 wait states at 120 MHz
— 2 wait states at 80 MHz
— 1 wait state at 60 MHz
Flash memory line 128-bit wide with 8-bit ECC on 64-bit word (total 144 bits)
Accessed via a 64-bit wide bus for write and a 128-bit wide array for read operations
1-bit error correction, 2-bit error detection
1.6.6
On-chip SRAM with ECC
The MPC5643L SRAM provides a general-purpose single port memory.
ECC handling is done on a 32-bit boundary for data and it is extended to the address to have the highest possible diagnostic
coverage including the array internal address decoder.
The SRAM module provides the following features:
System SRAM: 128 KB
ECC on 32-bit word (syndrome of 7 bits)
— ECC covers SRAM bus address
1-bit error correction, 2-bit error detection
Wait states:
— 1 wait state at 120 MHz
— 0 wait states at 80 MHz and 60 MHz
1.6.7
Platform flash memory controller
The following list summarizes the key features of the flash memory controller:
Single AHB port interface supports a 64-bit data bus. All AHB aligned and unaligned reads within the 32-bit container
are supported. Only aligned word writes are supported.
Array interfaces support a 128-bit read data bus and a 64-bit write data bus for each bank.
Code flash (bank0) interface provides configurable read buffering and page prefetch support.


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