1-Mbit (128K x 8) Static RAM

CY7C1019DV33

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

•

408-943-2600

Document #: 38-05481 Rev. *E

Revised December 14, 2010

Features

• Pin- and function-compatible with CY7C1019CV33

• High speed

• Low Active Power

• Low CMOS Standby Power

• 2.0V Data retention

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Center power/ground pinout

• Easy memory expansion with CE and OE options

• Available in Pb-free 32-pin 400-Mil wide Molded SOJ,

32-pin TSOP II and 48-ball VFBGA packages

Functional Description[1]

The CY7C1019DV33 is a high-performance CMOS static

RAM organized as 131,072 words by 8 bits. Easy memory

expansion is provided by an active LOW Chip Enable (CE), an

active LOW Output Enable (OE), and three-state drivers. This

device has an automatic power-down feature that significantly

reduces power consumption when deselected.

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing Write

Enable (WE) HIGH. Under these conditions, the contents of

the memory location specified by the address pins will appear

on the I/O pins.

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE LOW, and WE LOW).

The CY7C1019DV33 is available in Pb-free 32-pin 400-Mil

wide Molded SOJ, 32-pin TSOP II and 48-ball VFBGA

packages.

Logic Block Diagram

COLUMN

DECODER

INPUTBUFFER

POWER

DOWN

WE

OE

CE

128K × 8

ARRAY

Note

1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com

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