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SX8723CWLTDT Datasheet(PDF) 10 Page - Semtech Corporation |
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SX8723CWLTDT Datasheet(HTML) 10 Page - Semtech Corporation |
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10 / 67 page  www.semtech.com/products/ Page 10 ADVANCED COMMUNICATIONS & SENSING DATASHEET SX8723C ZoomingADC for sensing data acquisition Revision 1.01 January 2011 © Semtech 2.1.2 I2C interface timings (1) All timings specifications are referred to VILmin and VIHmax voltage levels defined for the SCL and SDA pins. (2) The digital interface is reset if the SCL is low more than tSCLTO duration. This is the default mode at startup. The timeout can be disabled by register setting. (3) A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system. (4) The device internally provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. (5) Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times according to Table 6 are allowed. Table 6. Digital interface Parameter Symbol STANDARD-MODE FAST-MODE Unit Min Typ Max Min Typ Max I2C TIMING SPECIFICATIONS Note 1 SCL clock frequency fSCL 0 100 0 400 kHz SCL timeout ( optional mode ) Note 2 tSCLTO 35 35 ms SCL Low Pulsewidth tL 4.7 1.3 μs SCL High Pulsewidth tH 4.0 0.6 μs Start Condition Hold Time tSCH 0.6 0.6 μs Data Setup Time tDS 250 100 Note 3 ns Data Hold Time tDH 0 Note 4 3.45 0 0.9 μs Setup Time for Repeated Start tRSU 4.7 0.6 μs Stop Condition Setup Time tPSU 4.0 0.6 μs Bus Free Time between a STOP Condition and a START Condition tBF 4.7 1.3 μs Pulsewidth of Spike Suppressed tSUP 100 100 ns Capacitive load for each bus line CB 400 400 pF Noise margin at the LOW level for each connected device (including hysteresis) VnL 0.1VBATT 0.1VBATT V Noise margin at the HIGH level for each connected device (including hysteresis) VnH 0.2VBATT 0.2VBATT V |
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