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LS7766 Datasheet(PDF) 6 Page - LSI Computer Systems

Part # LS7766
Description  32-BIT SINGLE- AXIS/DUAL-AXIS QUADRATURE COUNTER
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Manufacturer  LSI [LSI Computer Systems]
Direct Link  http://www.lsicsi.com
Logo LSI - LSI Computer Systems

LS7766 Datasheet(HTML) 6 Page - LSI Computer Systems

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x0/_x1 Input. The x0/_x1 input selects between axis-0
and axis-1 for Read and Write operations. A low at this
input selects axis-0 while a high selects axis-1.
RD/ Input. A low on RD/ input accesses an addressed
register(s) for read and places the data on the databus,
DB<15:0> in accordance with Table 1 and Table 2.
CS/ Input. A low on the CS/ input enables the chip for
read or write operation. When the CS/ input is high,
read and write operations are disabled and the databus,
DB<15:0> is placed in a high impedance state.
WR/ Input. A low pulse on the WR/ input writes the data
on the databus, DB<15:0> into the addressed register
according to Table 1 and Table 2. The write operation
is completed at the trailing edge of the WR/ pulse.
PCKI, PCKO. Input, Output. A clock applied at PCKI in-
put is used for validating the logic states of the A and B
quadrature clocks and the INDX/ input. Alternatively, a
crystal oscillator connected between PCKI and PCKO
can be used to generate the filter clock.
The PCK input frequency, fPCK is divided down by a fac-
tor of 1 or 2 according to bit7 of MCR0. The resultant
clock is used to sample the logic levels of the A, the B
and the INDX inputs. If a logic level at any of these
inputs remains stable for a minimum of two filter clock
periods, it is validated as a correct logic state.
The PCKI input is common to both axes, but the filter
clock frequency for any axis is set by its associated
MCR0 register.
In non-quadrature mode, no filter clock is used and the
PCKI input should be connected to either VDD or GND.
x0A, x0B Inputs. These are the A and B count inputs in
axis-0. These inputs can be configured to function either
in quadrature mode or in non-quadrature mode. The con-
figuration is made through MCR0. In quadrature mode,
A and B clocks are 90 degrees out of phase such as the
output from an Incremental Encoder. When A leads B
in phase, the CNTR counts up and when B leads A
in phase, the CNTR counts down.
In non-quadrature mode, A serves as the count input
while B controls the count direction. When B is
high,
positive transitions at the A input causes the CNTR to
count
up. Conversely, when B is low, the positive transi-
tion at the A input causes the CNTR to count
down.
In quadrature mode, A and B inputs are sampled by an
internal filter clock generated from the PCKI input. In
non-quadrature mode, A and B inputs are not sampled
and the count clocks are applied to the CNTR, bypassing
the filter circuit.
x1A , x1B:
These are the A and B inputs corresponding to axis-1, .
Functionally, they are identical with the A and B inputs
of axis-0.
x0INDX/ Input. The INDX/ input in axis-0. The INDX/ in-
put can be configured to function as load_CNTR or re-
set_CNTR or load_ODR input via MCR0. In quadrature
mode the INDX/ input can be configured to operate in
either synchronous or asynchronous mode. In the syn-
chronous mode the INDX/ input is sampled with the
same filter clock used for sampling the A and the B in-
puts and must satisfy the phase relationship with A and
B in which INDX/ is at the active level during a mini-
mum of a quarter cycle of both A and B high or both A
and B low. The active level of the INDX/ input is logic
low.
In non-quadrature mode the INDX/ input is un-
conditionally set to the asynchronous mode. In the
asynchronous mode the INDX/ input is not sampled
and can be applied in any phase relationship with re-
spect to the A and B inputs.
The INDX/ input can be either enabled or disabled in
both quadrature and non-quadrature modes.
x1INDX/. The INDX/ input corresponding to axes-1.
Functionally, it is identical with the INDX/ input of
axis-0.
IO16/ Input. When low, hex databus configuration is in-
voked in accordance with Table 2. When high, octal da-
tabus configuration is invoked in accordance with Ta-
ble 1. This input has an internal pull-up.
x0FLGa Output. The FLGa output in axis-0. The FLGa
output is configured by MCR1 register to function as
Carry and/or Borrow and/or Compare and/or Index flag.
A Carry flag is generated when the CNTR overflows, a
Borrow flag is generated when the CNTR underflows, a
Compare flag is generated by the condition, CNTR =
IDR and Index flag is generated when Index input is at
active level. The FLGa output can be configured to pro-
duce outputs in either latched mode or instantaneous
mode. In the latched mode when the selected event of
Carry or Borrow or Compare or index has taken place,
FLGa switches low and remains low until the status reg-
ister, STR is cleared. In the instantaneous mode, a neg-
ative pulse is generated instantaneously when the
event takes place. The FLGa output can be disabled to
remain at a fixed logic high.
x1FLGa Output. The FLGa output corresponding to
axes-1. Functionally, it is identical with the FLGa output
of axis-0.
7766-110806-6


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