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XE8802 Datasheet(PDF) 4 Page - Semtech Corporation |
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XE8802 Datasheet(HTML) 4 Page - Semtech Corporation |
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4 / 193 page  © Semtech 2006 www.semtech.com 1-2 XE8802 Sensing Machine Data Acquisition MCU with ZoomingADC™ and LCD driver 1.1 Top schematic The top-level block schematic of the circuit is shown in Figure 1-1. The heart of the circuit consists of the Coolrisc816 CPU core. This core includes an 8x8 multiplier and 16 internal registers. The bus controller generates all control signals for access to all data registers other than the CPU internal registers. The reset block generates the adequate reset signals for the rest of the circuit as a function of the set-up contained in its control registers. Possible reset sources are the power-on-reset (POR), the external pin NRESET, the watchdog (WD), a bus error detected by the bus controller or a programmable pattern on Port A. Different low power modes are implemented. The clock generation and power management block sets up the clock signals and generates internal supplies for different blocks. The clock can be generated from the RC oscillator (this is the start-up condition), the crystal oscillator (XTAL) or an external clock source (given on the XIN pin). The test controller generates all set-up signals for different test modes. In normal operation, it is used as a set of 8 low power data registers. If power consumption is important for the application, the variables that need to be accessed frequently should be stored in these registers rather than in the RAM. The IRQ handler routes the interrupt signals of the different peripherals to the IRQ inputs of the CPU core. It allows masking of the interrupt sources and it flags which interrupt source is active. Events are generally used to restart the processor after a HALT period without jumping to a specified address, i.e. the program execution resumes with the instruction following the HALT instruction. The EVN handler routes the event signals of the different peripherals to the EVN inputs of the CPU core. It allows masking of the interrupt sources and it flags which interrupt source is active. The Port B is an 8-bit parallel IO port with analog capabilities. The URST, UART, PWM and CMPD block also make use of this port. The instruction memory is a 22-bit wide flash or ROM memory depending on the circuit version. In case of the ROM version, the VPP and NFASTREAD pins are not used. ROM versions have 8k instruction memory. Flash versions have 8k or 4k instruction memories depending on the selected operation speed. The data memory on this product is a 1024 byte SRAM. The Acquisition Chain is a high-resolution acquisition path with the 16+10 bits ZoomingADC ™. The VMULT (voltage multiplier) powers a part of the Acquisition Chain. The SPI is a serial interface with a master or slave configuration capability. When unused, the 4 SPI pads can be used as 4-bit wide general-purpose I/O port. The port A is an 8 bit parallel input port. It can also generate interrupts, events or a reset. It can be used to input external clocks for the timer/counter/PWM block. The Port D1 and the Port D2 are two general-purpose 8 bit parallel I/O ports. The LCD driver can support a direct drive display (up to 32 segments), or multiplex 1/2, 1/3, 1/4 displays (up to 120 segments). The driver contains an on chip low-power voltage generation device VGEN. The LCD lines can be used as additional I/O pins. The USRT (universal synchronous receiver/transmitter) contains some simple hardware functions in order to simplify the software implementation of a synchronous serial link. |
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