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LC72720 Datasheet(PDF) 7 Page - Sanyo Semicon Device

Part # LC72720
Description  Single-Chip RDS Signal-Processing System LSI
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Manufacturer  SANYO [Sanyo Semicon Device]
Direct Link  https://www.sanyo-av.com/us/
Logo SANYO - Sanyo Semicon Device

LC72720 Datasheet(HTML) 7 Page - Sanyo Semicon Device

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CCB Input Data Format
Caution: The bits labeled with an asterisk must be set to 0.
1. Synchronization protection (forward protection) method setting (4 bits): FS0 to FS3
FS3 = 0: If offset words in the correct order could not be detected continuously during the number of blocks specified
by FS0 to FS2, take that to be a lost synchronization state.
FS3 = 1: If blocks with uncorrectable errors were received consecutively during the number of blocks specified by
FS0 to FS2, take that to be a lost synchronization state.
No. 5602-7/14
LC72720, 72720M
Initial value: FS0 = 0, FS1 = 1, FS2 = 0, FS3 = 0
Initial value: BS = 0
F
F
F
S
S
S
Condition for detecting lost synchronization
0
1
2
0
0
0
If 3 consecutive blocks matching the FS3 condition are received.
1
0
0
If 4 consecutive blocks matching the FS3 condition are received.
0
1
0
If 5 consecutive blocks matching the FS3 condition are received.
1
1
0
If 6 consecutive blocks matching the FS3 condition are received.
0
0
1
If 8 consecutive blocks matching the FS3 condition are received.
1
0
1
If 10 consecutive blocks matching the FS3 condition are received.
0
1
1
If 12 consecutive blocks matching the FS3 condition are received.
1
1
1
If 16 consecutive blocks matching the FS3 condition are received.
2. Synchronization detection method setting (1 bit): BS
BS
Synchronization detection conditions
0
If, during 3 blocks, 2 blocks of offset words were detected in the correct order.
1
If the offset words were detected in the correct order in 2 consecutive blocks.
[1] CCB address 6A
[2] CCB address 6B
IN1 data, first bit
IN2 data, first bit
(11) Circuit control
(5) Error correction method setting
(4) RAM write control
(3) Synchronization and RAM address reset
(2) Synchronization detection method setting
(1) Synchronization protection method setting
(10) Test mode settings
(9) Output pin settings
(8) RDS/RBDS selection
(7) Demodulation circuit phase control
(6) Crystal oscillator frequency selection
(11) Circuit control


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