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LC66512B Datasheet(PDF) 5 Page - Sanyo Semicon Device |
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LC66512B Datasheet(HTML) 5 Page - Sanyo Semicon Device |
5 / 28 page Main differences between the LC66E5316, LC66P5316, and LC6653XX Series Note: * Although the microcontroller will remain in hold mode if the RES pin is set low while it is in hold mode, always use the reset start sequence (after switching HOLD from low to high, switch RES from low to high) when clearing hold mode. Also a current of about 100 µA flows from the RES pin when it is low. This increases the hold mode current drain by about 100 µA. See the data sheets for the individual products for details on other differences. System Block Diagram No. 5489-5/28 LC66P5316 Item LC6653XX Series (mask version) LC66E5316 LC66P5316 Differences in the main characteristics –30 to +70°C +10 to +40°C –30 to +70°C • Operating temperature range 3.0 to 5.5 V/0.95 to 10 µs 4.5 to 5.5 V/0.95 to 10 µs 4.0 to 5.5 V/0.92 to 10 µs • Operating supply voltage/operating (When the main oscillator is (When the main oscillator is (When the main oscillator is frequency (cycle time) operating) operating) operating) 3.0 to 5.5 V/25 to 127 µs 4.5 to 5.5 V/25 to 127 µs 4.0 to 5.5 V/25 to 127 µs (When the sub-oscillator is operating) (When the sub-oscillator is operating) (When the sub-oscillator is operating) Typical: 10 µA Typical: 10 µA • Input high-level current (RES) Maximum: 1 µA (normal operation and halt mode) (normal operation and halt mode) Hold mode: 1 µA maximum Hold mode: 1 µA maximum • Input low-level current (RES) Maximum: 1 µA Typical: 100 µA Typical: 100 µA • Current drain (Operating at 4 MHz) (Operating at 32 kHz) Typical: 10 nA, maximum: 10 µA Larger than that for the mask versions Larger than that for the mask versions (Halt mode at 4 MHz) Typical: 10 nA, maximum: 10 µA* Typical: 10 nA, maximum: 10 µA* (Halt mode at 32 kHz) (Hold mode) Port output types at reset The output type specified in Open-drain outputs Open-drain outputs the options Package • DIP48S • DIC52S window package • DIP48S • QFP48E • QFC48 window package • QFP48E SYSTEM CONTROL RAM STACK (512W) SP E A OTP ROM (16KB) PROM control PC POUT0 A0 to A13 D0 to D7 SI0 SO0 SCK0 INT0 CE DASEC VPP/OE EPMOD TA INT1, INT2 PIN1, POUT1 INVxO INVxI (x=0 to 4) FLAG INTERRUPT CONTROL MPX MPX TIMER1 MPX TIMER0 SERIAL I/O 0 PE PD PC E M R D P Y D P X D P L D P H P0 P1 P2 P3 P4 P5 P6 DS1 DS0 P8 CZ ALU RES XT1 XT2 AN1 to 4 TEST OSC1 OSC2 HOLD ADC SI1 SO1 SCK1 SERIAL I/O 1 PRESCALER |
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