5

SY89833L

Micrel, Inc.

M9999-082407

hbwhelp@micrel.com or (408) 955-1690

August 2007

TIMING DIAGRAM

IN

/Q

Q

EN

/IN

V

Symbol

Parameter

Condition

Min

Typ

Max

Units

f

MAX

Maximum Frequency

V

2.0

GHz

t

pd

Propagation Delay

IN-to-Q

V

400

500

600

ps

IN-to-Q

V

330

440

530

ps

t

SKEW

Within-Device Skew

Note 8

520

ps

Part-to-Part Skew

Note 9

200

ps

t

S

Set-Up Time

EN to IN, /IN

Note 10

300

ps

t

H

Hold Time

EN to IN, /IN

Note 10

500

ps

t

JITTER

Data

Random Jitter (RJ)

Note 11

1ps

RMS

Deterministic Jitter (DJ)

Note 12

10

ps

PP

Clock

Cycle-to-Cycle Jitter

Note 13

1ps

RMS

Total Jitter (TJ)

Note 14

10

ps

PP

t

Output Rise/Fall Times

At full output swing.

60

110

190

ps

(20% to 80%)

Notes:

7.

High-frequency AC parameters are guaranteed by design and characterization.

8.

Within device skew is measured between two different outputs under identical input transitions.

9.

Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective

inputs.

10. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications,

set-up and hold times do not apply.

13. Cycle-to-cycle jitter definition: The variation period between adjacent cycles over a random sample of adjacent cycle pairs. t

where T is the time between rising edges of the output signal.

than the specified peak-to-peak jitter value.