4

SY89823L

Micrel, Inc.

M9999-091908

hbwhelp@micrel.com or (408) 955-1690

LVCMOS/LVTTL V

Symbol

Parameter

Condition

Min

Typ

Max

Units

V

IH

Input HIGH Voltage

2.0

——

V

V

IL

Input LOW Voltage

——

0.8

V

I

IH

Input HIGH Current

+20

—–250

µA

I

IL

Input LOW Current

——

–600

µA

Symbol

Parameter

Condition

Min

Typ

Max

Units

Maximum Operating Frequency

500

——

MHz

Propagation Delay

CLK-to-Q

Note 7

0.8

—

1.3

ns

SEL-to-Q

Note 7

0.8

1.2

1.7

ns

Within-Device Skew

Note 8

——

50

ps

Part-to-Part Skew

Note 9

——

200

ps

Minimum Input Swing

Note 10

600

——

mV

LVPECL_CLK

Common Mode Range

Note 11

–1.5

—–0.4

V

LVPECL_CLK

OE Set-Up Time

Note 12

1.0

——

ns

OE Hold Time

0.5

——

ns

Output Rise/Fall Time (20% – 80%)

300

—

700

ps

Cycle-to-Cycle Jitter

Note 13

Notes:

5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

6. High-frequency AC-parameters are guaranteed by design and characterization.

7. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the

differential output signals.

8. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the

same voltage and temperature.

9. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same

voltage and temperature.

12. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures outputs remain disabled during the

next clock cycle. OE LOW-to-HIGH transition enables normal operation of the next input clock.

output signal.