6

SY89531L

Micrel, Inc.

M9999-010808

hbwhelp@micrel.com or (408) 955-1690

V

Symbol

Parameter

Condition

Min

Typ

Max

Units

Xtal Input Frequency Range

Note 8

14

—

18

MHz

Output Frequency Range

w/Internal VCO

33.33

—

500

MHz

w/External VCO

——

622.08

MHz

Internal VCO Frequency Range

600

—

1000

MHz

External VCO Frequency

——

1250

MHz

Within Device Skew

——

50

ps

Note 9

Within-Bank PECL

——

50

ps

Within-Bank HSTL

——

75

ps

Between Banks

——

150

ps

Part-to-Part Skew

Note 10

——

200

ps

Maximum PLL Lock Time

——

10

ms

Cycle-to-Cycle Jitter

(Pk-to-Pk)

Note 11

—

25

—

ps

Period Jitter

(RMS)

Note 12

——

50

ps

Minimum Pulse Width

50

——

ns

Target PLL Loop Bandwidth

Feedback Divider Ratio: 72

Note 13

—

1.0

—

MHz

Feedback Divider Ratio: 34

Note 13

—

2.0

—

MHz

45

50

55

%

Output Rise/Fall Time

(20% to 80%)LVPECL_Out

—

250

450

ps

HSTL_Out

100

—

450

ps

Note 14

——

10

ns

5

——

ns

5

——

ns

1

——

VCO

clock cycle

FSEL-to-Valid Output Transition Time

——

1

µs

500

——

ps

Note 8.

Fundamental mode crystal.

Note 9.

The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the

same voltage and temperature.

Note 10. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same

voltage and temperature.

Note 11. Cycle-to-cycle jitter definition: The variation in period between adjacent cycles over a random sample of adjacent cycle pairs. T

T

Note 12. Period Jitter definition: For a specified amount of time (i.e., 1ms), there are N periods of a signal, and T

that signal. Period jitter is defined as the variation in the period of the output signal for corresponding edges relative to T

Note 13. Using recommended loop filter components. See

“Functional Description, External Loop Filter Considerations.”

Note 14. See

“Timing Diagrams.”

AC ELECTRICAL CHARACTERISTICS