SY87729L

9

Micrel, Inc.

M9999-062807

hbwhelp@micrel.com or (408) 955-1690

MicroWire™ Interface

This standard bit-serial interface eases interfacing the

SY87729L to microcontrollers. The SY87729L accepts one

data bit on PROGDI per rising edge on PROGSK. The data

is ignored when PROGCS is inactive low. When PROGCS

is active high, bits are shifted into the SY87729L. The falling

edge of PROGCS then initiates acquisition of the output

frequency defined by the 32-bit program just loaded into

the SY87729L.

This means that, if the user wishes to re-acquire based

on the same program, PROGCS needs to toggle high then

low.

Programming

To program the SY87729L to generate a certain

frequency:

1. Determine the required values of the programming

parameters, as summarized in Table 6.

2. Set PROGCS active high.

3. Shift in each of the 32 bits, as per Table 6. The fields

are loaded in sequence, from the first row to the last

row. For each multi-bit field, the most significant bit is

shifted in first. Shift the bits in through PROGDI,

clocking them with PROGSK edges.

4. Set PROGCS inactive low.

5. Wait for LOCKED to assert high.

Field

# Bits

Reference

Preamble

4

always "0000"

qp

5

Section: Gating the P/P-1 Divider

qpm1

5

Section: Gating the P/P-1 Divider

divsel

4

Table 1

mfg.

3

always "000"

PostDivSel

5

Table 5

NdivSel

3

Table 4

MdivSel

3

Table 3

Table 6. Programming Sequence

The SY87729L generates exact frequencies for common

serial data streaming protocols. Summary programming

information appears in the next section. The SY87729L also

virtually anything within its range of operation, all from a

27.000MHz reference. Details about how to program the

SY87729L in the general case, including derivation of

application, appear in an applications note.

P Divider

The output of the wrapper synthesizer is post divided

down before appearing at the CLKOUT± pins. Notice that,

given the range of the wrapper VCO (540MHz to 729MHz)

and the maximum and minimum division ratios of the P

divider (2 to 60, as shown in Table 5), the minimum and

maximum frequency of CLKOUT± is 9MHz and 364.5MHz

respectively.

PostDivSel Bit

43210

Divisor

00000

2

00001

3

00010

2

00011

3

00100

4

00101

5

00110

6

00111

7

01000

8

01001

9

01010

10

01011

11

01100

12

01101

13

01110

14

01111

15

10000

16

10001

18

10010

20

10011

22

10100

24

10101

26

10110

28

10111

30

11000

32

11001

36

11010

40

11011

44

11100

48

11101

52

11110

56

11111

60

Table 5. Setting to Program the Division Ratio

of the P Divider

The divisor value is selected via MicroWire™. The 5-bit

PostDivSel register determines the divisor value. It is set as

per Table 5. The SY87729L does not guarantee a 50%

duty cycle output. It is designed to provide well-timed rising

edges only.