Micrel, Inc.

SY69753AL

August 2007

3

M9999-082107-E

Pin Description

Inputs

Pin Number

Pin Name

Type

Pin Name

2

3

RDINP

RDINN

Differential

PECL

Serial Data Input: These built-in line receiver inputs are connected to the differential receive

serial data stream. An internal receive PLL recovers the embedded clock (RCLK) and data

(RDOUT) information.

5

REFCLK

TTL Input

Reference Clock: This input is used as the reference for the internal frequency synthesizer

and the "training" frequency for the receiver PLL to keep it centered in the absence of data

coming in on the RDIN inputs.

26

CD

PECL Input

Carrier Detect: This input controls the recovery function of the Receive PLL and can be driven

by the carrier detect output of optical modules or from external transition detection circuitry.

When this input is HIGH, the input data stream (RDIN) is recovered normally by the Receive

PLL. When this input is LOW the data on the inputs RDIN will be internally forced to a

constant LOW, the data outputs RDOUT will remain LOW, the Link Fault Indicator output

LFIN forced LOW and the clock recovery PLL forced to look onto the clock frequency

generated from REFCLK.

32

25

DIVSEL1

DIVSEL2

TTL Input

Divider Select: These inputs select the ratio between the output clock frequency

(RCLK/TCLK) and the REFCLK input frequency as shown in the “Reference Frequency

Selection” table.

16

CLKSEL

TTL Input

Clock Select: This input is used to select either the recovered clock of the receiver PLL

(CLKSEL = HIGH) or the clock of the frequency synthesizer (CLKSEL = LOW) to the TCLK

outputs.

Outputs

Pin Number

Pin Name

Type

Pin Name

31

LFIN

TTL Output

Link Fault Indicator: This output indicates the status of the input data stream RDIN. Active

HIGH signal is indicating when the internal clock recovery PLL has locked onto the incoming

data stream. LFIN will go HIGH if CD is HIGH and RDIN is within the frequency range of the

Receive PLL (1000ppm) and will be alternating if not. LFIN is an asynchronous output.

23

24

RDOUTN

RDOUTP

Differential

PECL

Receive Data Output: These ECL 100K outputs represent the recovered data from the input

data stream (RDIN). This recovered data is specified against the rising edge of RCLK.

20

21

RCLKN

RCLKP

Differential

PECL

Clock Output: These ECL 100K outputs represent the recovered clock used to sample the

recovered data (RDOUT).

18

17

TCLKP

TCLKN

Differential

PECL

Clock Output: These ECL 100K outputs represent either the recovered clock (CLKSEL =

HIGH) used to sample the recovered data (RDOUT) or the transmit clock of the frequency

synthesizer (CLKSEL = LOW).

9

10

PLLSP

PLLSN

Clock Synthesis PLL Loop Filter: External loop filter pins for the clock synthesis PLL.

14

15

PLLRN

PLLRP

Clock Recovery PLL Loop Filter: External loop filter pins for the receiver PLL.

Power and Ground

Pin Number

Pin Name

Type

Pin Name

27, 28

VCC

Power Supply.

(1)

29

30

VCCA

Analog Power Supply Voltage.

(1)

19, 22

VCCO

Output Supply Voltage.

(1)

12, 13

GND

Ground.

1, 4, 6, 7, 8

NC

No connect.

11

GNDA

Analog Ground.

Note:

1. VCC, VCCA, VCCO must be the same value.