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MIC1232MY Datasheet(PDF) 2 Page - Micrel Semiconductor |
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MIC1232MY Datasheet(HTML) 2 Page - Micrel Semiconductor |
2 / 6 page MIC1232 2 January 2006 MIC1232 Micrel, Inc. Pin Configuration 1 2 3 4 TD TOL GND 8 7 6 5 VCC RST RST MIC1232 PBRST ST 8-Pin PDIP Package 8-Pin SOIC Package Pin Description Pin Number Pin Name Pin Function 1 /PBRST Pushbutton Reset Input: This input is debounced and can be driven with ex- ternal logic signals or by means of a mechanical pushbutton to actively force a reset. All pulses less than 1ms in duration on the /PBRST pin are ignored, whereas, any pulse with a duration of 20ms or greater is guaranteed to cause a reset. 2 TD Time Delay input: This input selects the timebase used by the watchdog timer. When TD = 0V, the watchdog timeout period is set to a normal value of 150ms, when TD = open, the watchdog timeout period is et to a nominal value of 600ms and when TD = VCC, the watchdog period is 1.2s nominally. 3 TOL Tolerance Select Input: Selects whether 5% or 10% of VCC is used as the reset threshold voltage. When TOL = 0V, the 5% tolerance level is selected and when TOL = VCC, a 10% tolerance level is selected. 4 GND IC ground pin, 0V reference 5 RST RST is asserted high if either VCC goes below the reset threshold, the watch- dog times out or /PBRST is pulled low for a minimum of 20ms. RST remains asserted for one reset timeout period after VCC exceeds the reset threshold or after the watch times out or after /PBRST goes high. 6 /RST /RST is asserted low if either VCC goes below the reset threshold, the watch- dog times out or /PBRST is pulled low for a minimum of 20ms. /RST remains asserted for one reset timeout period after VCC exceeds the reset threshold or after the watch times out or after /PBRST goes high. Open-drain output 7 /ST Input to watchdog timer. If /ST does not see a transition from high to low within the watchdog timeout period, RST and /RST will be asserted. 8 VCC Primary supply input, +5V |
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