LC651204N datasheet(34/35 Pages) SANYO

Part #	LC651204N

Description	4-Bit Single-Chip Microcontrollers for Small-Scale Control Applications

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Manufacturer	SANYO [Sanyo Semicon Device]

Direct Link	https://www.sanyo-av.com/us/

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34 / 35 page

No. 5190-34/35

LC651204N/F/L, LC651202N/F/L

Instruction code

Modified

Mnemonic

Operation

Description

status

Notes

D7 D6 D5 D4

D3 D2 D1 D0

flags

Load DPH with Zero and

DPH ← 0

Loads 0 into DPH and the

LDZ data

DPL with immediate data

1

0

I3

I2

I1

I0

1

DPL ← I3 I2 I1 I0

immediate data I3I2I1I0 into DPL.

respectively

LHI data

Load DPH with immediate

0

1

0

I3

I2

I1

I0

1

DPH ← I3 I2 I1 I0

Loads the immediate data I3 I2 I1 I0

data

into DPH.

IND

Increment DPL

1

0

1

0

1

DPL ← (DPL) + 1

Increments the contents of DPL. ZF

DED

Decrement DPL

1

0

1

DPL ← (DPL) – 1

Decrements the contents of DPL. ZF

TAL

Transfer AC to DPL

1

0

1

DPL ← (AC)

Moves the contents of AC to DPL.

TLA

Transfer DPL to AC

1

0

1

0

1

AC

← (DP

L)

Moves the contents of DPL to AC. ZF

XAH

Exchange AC with DPH

0

1

0

1

(AC)

↔ (DP

H)

Exchanges the contents of AC

and DPH.

XAt

t1

t0

Exchanges the contents of AC

XA0

Exchange AC with working

1

0

1

(AC)

↔ (A0)

and the working register A0, A1,

XA1

register At

1

0

1

0

1

(AC)

↔ (A1)

A2, or A3 specified by t1t0.

XA2

1

0

1

0

1

(AC)

↔ (A2)

XA3

1

0

1

0

1

(AC)

↔ (A3)

XHa

Exchange DPH with working

a

Exchanges the contents of DPH

XH0

register Ha

1

0

1

(DPH) ↔ (H0)

and the working register H0 or H1

XH1

1

0

1

(DPH) ↔ (H1)

specified by a.

XLa

Exchange DPH with working

a

Exchanges the contents of DPL

XL0

register Ha

1

0

1

(DPL) ↔ (L0)

and the working register L0 or L1

XL1

1

0

1

(DPL) ↔ (L1)

specified by a.

SFB flag

Set flag bit

0

1

0

1

B3 B2 B1 B0

1

Fn

← 1

Sets the flag specified by B3 B2

B1 B0 to 1.

Clears the flag specified by B3

B2 B1 B0 to 0.

RFB flag

Reset flag bit

0

1

B3 B2 B1 B0

1

Fn

← 0

ZF

0

1

0

1 P10 P9 P8

PC

← P

10 P9 P8 P7 P6

Jumps to the location specified

JMP addr

Jumping in the current bank

P7 P6 P5 P4

P3 P2 P1 P0

2

P5 P4 P3 P2 P1 P0 by the immediate data P10 P9

P8 P7 P6 P5 P4 P3 P2 P1 P0.

JPEA

Jumping current page

1

0

1

0

1

PC0 to 7 ← (E, AC)

Jumps to the location given by

modified by E and AC

replacing the lower 8 bits of the

PC with E and AC.

CZP addr

Call subroutine in the zero

1

0

1

P3 P2 P1 P0

1

STACK

← (PC) + 1

page

PC10 to 6 , PC1 to 0 ← 0 Calls a subroutine on page 0.

PC5 to 2 ← P3 P2 P1 P0

CAL addr

Call subroutine

1

0

1

0

1 P10 P9 P8

2

STACK

← (PC) + 2

Calls a subroutine.

RT

Return from subroutine

0

1

0

1

0

1

PC

← (STACK)

Returns from a subroutine.

RTI

Return from interrupt routine

0

1

0

1

0

1

PC

← (STACK)

Returns from an interrupt

ZF

CF

CF, ZF

← CSF, ZSF

handling routine.

Specifies a pseudo I/O port

BANK

Change bank

1

0

1

and changes the bank.

BAt addr

Change bank

0

1

0

t1

t0

2

PC7 to 0 ← P7 P6 P5 P4

Branches to the location on the

P7 P6 P5 P4

P3 P2 P1 P0

same page specified by P7 to P0

if ACt = 1

if the bit in AC specified by the

immediate data t1t0 is 1.

BNAt addr

Branch on no AC bit

0

1

0

t1

t0

2

PC7 to 0 ← P7 P6 P5 P4

Branches to the location on the

P7 P6 P5 P4

P3 P2 P1 P0

same page specified by P7 to P0

if ACt = 0

if the bit in AC specified by the

immediate data t1t0 is 0.

BMt addr

Branch on M bit

0

1

0

1

t1

t0

2

PC7 to 0 ← P7 P6 P5 P4

Branches to the location on the

P7 P6 P5 P4

P3 P2 P1 P0

same page specified by P7 to P0

if [M(DP, t1 t0)] = 1

if the bit in M(DP) specified by

the immediate data t1 t0 is 1.

BNMt addr

Branch on no M bit

0

1

0

1

t1

t0

2

PC7 to 0 ← P7 P6 P5 P4

Branches to the location on the

P7 P6 P5 P4

P3 P2 P1 P0

same page specified by P7 to P0

if [M(DP, t1 t0)] = 0

if the bit in M(DP) specified by

the immediate data t1 t0 is 0.

BPt addr

Branch on Port bit

0

1

0

t1

t0

2

PC7 to 0 ← P7 P6 P5 P4

Branches to the location on the

P7 P6 P5 P4

P3 P2 P1 P0

same page specified by P7 to P0

if [P(DPL, t1 t0)] = 1

if the bit in port P(DPL) specified

by the immediate data t1 t0 is 1.

BNPt addr

Branch on no Port bit

0

1

0

t1

t0

2

PC7 to 0 ← P7 P6 P5 P4

Branches to the location on the

P7 P6 P5 P4

P3 P2 P1 P0

same page specified by P7 to P0

if [P(DPL, t1 t0)] = 0

if the bit in port P(DPL) specified

by the immediate data t1 t0 is 0.

0

1

0

PC7 to 0 ← P7 P6 P5 P4

Branches to the location on the

BTM addr

Branch on timer

P7 P6 P5 P4

P3 P2 P1 P0

same page specified by P7 to P0 TMF

2

if TMF = 0

if TMF is 1. Also clears TMF.

then TMF

← 0

The flags are divided

into four groups, F0

to F3, F4 to F7, F8 to

F11, and F12 to F15.

ZF is set or cleared

according to the 4

bits included in the

specified flags.

Only valid for the

immediately

following JMP, I/O,

or branch instruction.

The mnemonics are

BA0

to

BA3,

reflecting the value

of t.

The mnemonics are

BNA0

to

BNA3,

reflecting the value

of t.

The mnemonics are

BM0

to

BM3,

reflecting the value

of t.

The mnemonics are

BNM0 to BNM3,

reflecting the value

of t.

The mnemonics are

BP0

to

BP3,

reflecting the value

of t.

The mnemonics are

BNP0

to

BNP3,

reflecting the value

of t.

Continued from preceding page.

Continued on next page.

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