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ZXCL5213V33H5TA Datasheet(PDF) 10 Page - Diodes Incorporated |
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ZXCL5213V33H5TA Datasheet(HTML) 10 Page - Diodes Incorporated |
10 / 14 page ZXCL SERIES Issue 8 - October 2007 10 www.zetex.com © Zetex Semiconductors plc 2007 Applications information (Cont) Power dissipation The maximum allowable power dissipation of the device for normal operation (Pmax), is a function of the package junction to ambient thermal resistance ( θ ja), maximum junction temperature (Tjmax), and ambient temperature (Tamb), according to the expression: Pmax = (Tjmax – Tamb) / θja The maximum output current (Imax) at a given value of Input voltage (VIN) and output voltage (VOUT) is then given by Imax = Pmax / (VIN - VOUT) The value of qja is strongly dependent upon the type of PC board used. Using the SC70 package it will range from approximately 280°C/W for a multi-layer board to around 450°C/W for a single sided board. It will range from 180°C/W to 300°C/W for the SOT23-5 package. To avoid entering the thermal shutdo wn state, Tjmax should be assumed to be 125°C and Imax less than the over-current limit,(IOLIM). Power derating for the SC70 and SOT23-5 packages is shown in the following graph. Capacitor selection and regulator stability The device is designed to operate with all types of output capacitor, including tantalum and low ESR ceramic. For stability over the full operating range from no load to maximum load, an output capacitor with a minimum value of 1 μF is recommended, although this can be increased without limit to improve load transient performance. Higher values of output capacitor will also reduce output noise. Capacitors with ESR less than 0.5V are recommended for best results. The dielectric of the ceramic capacitance is an important consideration for the ZXCL Series operation over temperature. Zetex recommends minimum dielectric specification of X7R for the input and output capacitors. For example a ceramic capacitor with X7R dielectric will lose 20% of its capacitance over a -40 C to 85 C temperature range, whereas a capacitor with a Y5V dielectric loses 80% of its capacitance at -40 C and 75% at 85 C. An input capacitor of 1 F (ceramic or tantalum) is recommended to filter supply noise at the device input and will improve ripple rejection. The input and output capacitors should be positioned close to the device, and a ground plane board layout should be used to minimise the effects of parasitic track resistance. Dropout voltage The output pass transistor is a large PMOS device, which acts like a resistor when the regulator enters the dropout region. The dropout voltage is therefore proportional to output current as shown in the typical characteristics. Ground current The use of a PMOS device ensures a low value of ground current under all conditions including dropout, start-up and maximum load. Power supply rejection and load transient response Line and Load transient response graphs are shown in the typical characteristics. These show both the DC and dynamic shift in the output voltage with step changes of input voltage and load current, and how this is affected by the output capacitor. If improved transient response is required, then an output capacitor with lower ESR value should be used. Larger capacitors will reduce over/ undershoot, but will increase the settling time. Best results are obtained using a ground plane layout to minimise board parasitics. -40 -20 0 20406080 100 0 100 200 300 400 500 SOT23 SC70 Derating Curve Temperature (°C) |
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