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TMS320C6A8167 Datasheet(PDF) 3 Page - Texas Instruments

Part # TMS320C6A8167
Description  TMS320C6A816x Integra DSPARM Processors
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

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TMS320C6A8168
TMS320C6A8167
www.ti.com
SPRS680 – OCTOBER 2010
1.2
Description
The C6A816x Integra™ DSP+ARM® Processors are a highly-integrated, programmable platform that
leverages TI's Integra™ technology to meet the processing needs of the following applications:
Medical/Industrial Vision Systems, High-End Test and Measurement, Tracking and Control, and
Medical/Biological Imaging.
The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating
systems support, rich user interfaces, and high processing performance through the maximum flexibility of
a fully integrated mixed processor solution. The device combines programmable digital signal processing
with an ARM® microprocessor and a highly-integrated peripheral set.
The C674x DSP core is the high-performance floating-point DSP generation in the TMS320C6000™ DSP
platform. The C674x floating-point DSP processor uses 32KB of L1 program memory and 32KB of L1 data
memory. Up to 32KB of L1P can be configured as program cache. The remaining is non-cacheable
no-wait-state program memory. Up to 32KB of L1D can be configured as data cache. The remaining is
non-cacheable no-wait-state data memory. The DSP has 128KB of L2 RAM, which can be defined as
SRAM, L2 cache, or a combination of both. All C674x L3 and off-chip memory accesses are routed
through an MMU.
Programmability is provided by an ARM® Cortex™-A8 RISC CPU with NEON™ extension, TI C674x VLIW
floating-point DSP core, and high-definition video/imaging coprocessors. The ARM® allows developers to
keep control functions separate from A/V algorithms programmed on the DSP and coprocessors, thus
reducing the complexity of the system software. The ARM® Cortex™-A8 32-bit RISC microprocessor with
NEON™ floating-point extension includes: 32K bytes (KB) of instruction cache; 32KB of data cache;
256KB of L2 cache; and 64KB of RAM.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections in this document and
the associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem
(HDVPSS), which provides output of simultaneous HD and SD analog video and dual HD video inputs; up
to two Gigabit Ethernet MACs (10/100/1000 Mbps) with GMII and MDIO interface; two USB ports with
integrated 2.0 PHY; PCIe® port x2 lanes GEN2 compliant interface, which allows the device to act as a
PCIe® root complex or device endpoint; one 6-channel McASP audio serial port (with DIT mode); two
dual-channel McASP audio serial ports (with DIT mode); one McBSP multichannel buffered serial port;
three UARTs with IrDA and CIR support; SPI serial interface; SD/SDIO serial interface; two I2C
master/slave interfaces; up to 64 General-Purpose I/O (GPIO); seven 32-bit timers; system watchdog
timer; dual DDR2/3 SDRAM interface; flexible 8/16-bit asynchronous memory interface; and up to two
SATA interfaces for external storage on two disk drives, or more with the use of a port multiplier.
The device also includes an SGX530 3D graphics engine (available only on the C6A8168 device) to
off-load 3D graphics processing tasks from the DSP core, making more DSP MIPS available for common
real-time signal processing algorithms. Additionally, it has a complete set of development tools for both the
ARM and DSP which include C compilers, a DSP assembly optimizer to simplify programming and
scheduling, and a Microsoft ® Windows® debugger interface for visibility into source code execution.
The device package has been specially engineered with Via Channel™ technology. This technology
allows 0.8-mm pitch PCB feature sizes to be used in this 0.65-mm pitch package, and substantially
reduces PCB costs. It also allows PCB routing in only two signal layers (four layers total) due to the
increased layer efficiency of the Via Channel™ BGA technology.
Copyright © 2010, Texas Instruments Incorporated
Device Summary
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