CSD86330Q3D

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SLPS264A – OCTOBER 2010 – REVISED DECEMBER 2010

RECOMMENDED PCB DESIGN OVERVIEW

There are two key system-level parameters that can be addressed with a proper PCB design: Electrical and

Thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief

description on how to address each parameter is provided.

Electrical Performance

The Power Block has the ability to switch voltages at rates greater than 10kV/µs. Special care must be then

taken with the PCB layout design and placement of the input capacitors, Driver IC, and output inductor.

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The placement of the input capacitors relative to the Power Block’s VIN and PGND pins should have the

highest priority during the component placement routine. It is critical to minimize these node lengths. As such,

ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 30).

The example in Figure 30 uses 6 × 10-µF ceramic capacitors (TDK Part # C3216X5R1C106KT or equivalent).

Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias

interconnecting both layers. In terms of priority of placement next to the Power Block, C5, C7, C19, and C8

should follow in order.

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should be connected to the Phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap

capacitor for the Driver IC will also connect to this pin.

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The switching node of the output inductor should be placed relatively close to the Power Block VSW pins.

Minimizing the node length between these two components will reduce the PCB conduction losses and

Thermal Performance

The Power Block has the ability to utilize the GND planes as the primary thermal path. As such, the use of

thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder

voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount

of solder attach that will wick down the via barrel:

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Intentionally space out the vias from each other to avoid a cluster of holes in a given area.

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Use the smallest drill size allowed in your design. The example in Figure 30 uses vias with a 10 mil drill hole

and a 16 mil capture pad.

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Tent the opposite side of the via with solder-mask.

In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and

manufacturing capabilities.

Figure 30. Recommended PCB Layout (Top Down)

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Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of

Missouri – Rolla

Copyright © 2010, Texas Instruments Incorporated

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