8

9145D–AUTO–05/10

ATA5021

4.

State Diagram

The kernel of the watchdog is a finite state machine. Figure 4-1 shows the state diagram with all

possible states and transmissions. Many transmissions are controlled by an internal timer. The

numbers for the time-outs are the same as on the pulse diagrams.

Figure 4-1.

State Diagram of the Finite State Machine

Short

Window

Enable

State

Short

Window

Disable

State

Long

Window

Disable

State

Long

Window

Disable

State

2. wedge is the detection of a signal edge on the wake-up pin after the deboucing time

3. trg_ok is valid for once cycle after the rising edge on trg_d

4. trg_err is valid if the low period of trg_d is too long

1. mode_d and trg_d are the debounced signals of the MODE and TRG pins

Notes:

Reset

Out

State

Mode

Switch

State

Reset

State

mode_d = 0

mode_d = 1

mode_d = 1

mode_d = 0

mode_d = 0

trg_ok

trg_d = 0

OR wedge

trg_ok

trg_d = 0

OR trg_err

OR trg_err

OR wedge