 |
 |
|
| AP7217A-33SG-13 |
|
|||||||||||||||||
 DIODES
|
| |||||||||||||||||
|
4 page 
AP7217A 3.3V 600mA CMOS LDO AP7217A Rev. 3 4 of 10 OCTOBER 2009 DS31423 © Diodes Incorporated Electrical Characteristics (TA = 25°C, CIN = 1µF, COUT = 1µF, VEN = VIN, unless otherwise noted) Symbol Parameter Test Conditions Min Typ. Max Unit IQ Quiescent Current IO = 0mA - 50 80 µA ISTB Standby Current VEN = Off VIN = 5.0V 15 25 µA Output Voltage Accuracy IO = 30mA, VIN = 5V 3.234 3.300 3.366 V VROUT VOUT Temperature Coefficient -40 °C to 85°C, I OUT = 30mA ±100 ppm / oC IOUT = 300mA 350 400 VDROPOUT Dropout Voltage IOUT = 600mA 800 900 mV IOUT Maximum Output Current VIN = 5.3V 600 mA ILIMIT Current Limit VIN = 5.3V 750 mA Ishort Short Circuit Current VIN = 5.3V 50 mA ∆V LINE/∆VIN/VOUT Line Regulation 4.3V ≤ V IN ≤ 5.5V; IOUT = 30mA 0.01 ±0.2 %/V ∆V OUT Load Regulation 1mA ≤ I OUT ≤ 100mA, VIN = 5.3V 15 50 mV PSRR Power Supply Rejection VIN = 4.3V+ 0.5Vp-pAC, IOUT = 50mA F = 1KHz 55 dB VEH Output ON 1.6 V VEL EN Input Threshold Output OFF 0.25 V IEN Enable Pin Current -0.1 0.1 µA VDF Detect fall voltage 3.23 3.3 3.37 V VD Hysteresis Range VHysteresis VDF x1.02 VDF x1.05 VDF x1.08 V IVDout VD Supply Current VDout = 0.5V VIN = 2.0V 3.0V 20 30 mA tRP VDOUT Delay Time VIN = 1.8V to VDF+ 1V 180 200 - mSec SOP-8L (Note 3) 134 θ JA Thermal Resistance Junction-to-Ambient SOP-8L-EP (Note 4) 82 ºC/W SOP-8L (Note 3) 28 θ JC Thermal Resistance Junction-to-Case SOP-8L-EP (Note 4) 12 ºC/W Notes: 3. Test condition for SOP-8L: Device mounted on FR-4 substrate PC board, 2oz copper, with minimum recommended pad layout. 4. Test condition for SOP-8L-EP: Device mounted on 2oz copper, minimum recommended pad layout on top & bottom layer with thermal vias, double sided FR-4 PCB. |
