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IC-MQEVALMQ1D Datasheet(PDF) 7 Page - IC-Haus GmbH |
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IC-MQEVALMQ1D Datasheet(HTML) 7 Page - IC-Haus GmbH |
7 / 39 page iC-MQ PROGRAMMABLE 9-BIT Sin/Cos INTERPOLATION IC WITH RS422 DRIVER Rev D4, Page 7/39 ELECTRICAL CHARACTERISTICS Operating Conditions: VDD = 4.3...5.5 V, Tj = -40 °C...125 °C, IBN calibrated to 200 µA, unless otherwise stated Item Symbol Parameter Conditions Unit No. Min. Typ. Max. 118 ∆ PHI12 Phase Error Calibration Step Width 0.63 ° 119 INL(PHI12) Integral Linearity Error of Phase Calibration limited test coverage (guaranteed by design) -0.8 0.8 ° 120 fin() Permissible Maximum Input Freq. analog signal path 200 kHz 121 Vout(X2) Output Voltage at X2 BIASEX = 10, I(X2) = 0, referenced to VRE- Fin12 95 100 105 % 122 Vin(X2) Permissible Input Voltage Range at X2 BIASEX = 11 0.5 VDDS − 2 V 123 Rin(X2) Input Resistance at X2 BIASEX = 11, RIN0(3:0) = 0x01, RIN12(3:0) = 0x01 20 27 30 kΩ Sine-To-Digital Conversion 201 AAabs Absolute Angle Accuracy referenced to 360° input signal, ideal waveform, quasi static signals, adjusted signal condition- ing, SELHYS = 0 0.9 1.8 ° 202 AArel Relative Angle Accuracy referenced to output period T (see Fig. 1), ideal waveform, quasi static signals; at 4 edges per period 10 % at 100 edges per period <0.5 10 % at 384 edges per period 10 % at 400 edges per period <2 10 % 203 AAR Repeatability see 201; VDD = const., Tj = const. 0.1 ° Line Driver Outputs PA, NA, PB, NB, PZ, NZ 501 Vs()hi Saturation Voltage hi Vs() = VDD - V(); SIK(1:0) = 00, I() = -1.2 mA 200 mV SIK(1:0) = 01, I() = -4 mA 200 mV SIK(1:0) = 10, I() = -20 mA 400 mV SIK(1:0) = 11, I() = -50 mA 700 mV 502 Vs()lo Saturation Voltage lo SIK(1:0) = 00, I() = 1.2 mA 200 mV SIK(1:0) = 01, I() = 4 mA 200 mV SIK(1:0) = 10, I() = 20 mA 400 mV SIK(1:0) = 11, I() = 50 mA 700 mV 503 Isc()hi Short-Circuit Current hi V() = 0 V; SIK(1:0) = 00 -4 -1.2 mA SIK(1:0) = 01 -12 -4 mA SIK(1:0) = 10 -60 -20 mA SIK(1:0) = 11 -150 -50 mA 504 Isc()lo Short-Circuit Current lo V() = VDD; SIK(1:0) = 00 1.2 4 mA SIK(1:0) = 01 4 12 mA SIK(1:0) = 10 20 60 mA SIK(1:0) = 11 50 150 mA 505 tr() Rise Time RL = 100 Ω to GND; SSR(1:0) = 00 5 20 ns SSR(1:0) = 01 5 40 ns SSR(1:0) = 10 20 140 ns SSR(1:0) = 11 50 350 ns 506 tf() Fall Time RL = 100 Ω to VDD; SSR(1:0) = 00 5 20 ns SSR(1:0) = 01 5 40 ns SSR(1:0) = 10 30 140 ns SSR(1:0) = 11 50 350 ns 507 Ilk()tri Leakage Current TRIHL(1:0) = 11 (tristate) 20 100 µA 508 IIk()rev Leakage Current reversed supply voltage 100 µA 509 Rin()cal Test Signal Source Impedance Op. modes Calibration 1, 2, 3 2.5 4 kΩ 510 I()cal Permissible Test Signal Load Op. modes Calibration 1, 2, 3 -3 3 µA 511 tclk()lo Clock Signal Low-Pulse Duration for CP, CPD, CPU Op. mode Mode 191/193; MTD = 0x0 110 ns MTD = 0x7 800 ns 512 tw()hi Duty Cycle referenced to output period T, see Fig. 1 50 % |
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