M48Z512A, M48Z512AY, M48Z512AV

Operating modes

Doc ID 5146 Rev 8

9/21

2.2

WRITE mode

The M48Z512A/Y/V is in the WRITE mode whenever W and E are active. The start of a

WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated

by the earlier rising edge of W or E.

The addresses must be held valid throughout the cycle. E or W must return high for a

contention; although, if the output bus has been activated by a low on E and G, a low on W

Table 3.

READ mode AC characteristics

Symbol

1.

or 3.0 to 3.6 V (except where noted).

M48Z512A/Y

–70

M48Z512A/Y/V

–85

Unit

Min

Max

Min

Max

READ cycle time

70

85

ns

Address valid to output valid

70

85

ns

Chip enable low to output valid

70

85

ns

Output enable low to output valid

35

45

ns

(2)

2.

Chip enable low to output transition

5

5

ns

(2)

Output enable low to output transition

5

5

ns

(2)

Chip enable high to output Hi-Z

30

35

ns

(2)

Output enable high to output Hi-Z

20

25

ns

Address transition to output transition

5

5

ns