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M48Z128 Datasheet(PDF) 9 Page - STMicroelectronics |
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M48Z128 Datasheet(HTML) 9 Page - STMicroelectronics |
9 / 20 page M48Z128, M48Z128Y, M48Z128V Operating modes Doc ID 2426 Rev 5 9/20 2.2 WRITE mode The M48Z128/Y/V is in the WRITE mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for minimum of tEHAX from E or tWHAX from W prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX or tEHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls. Figure 6. WRITE enable controlled, WRITE AC waveforms Note: Output enable (G) = high. Figure 7. Chip enable controlled, WRITE AC waveforms Note: Output enable (G) = high. AI01198 tAVAV tWHAX tDVWH DATA INPUT A0-A16 E W DQ0-DQ7 VALID tAVWH tAVEL tWLWH tAVWL tWLQZ tWHDX tWHQX AI01199 tAVAV tEHAX tDVEH A0-A16 E W DQ0-DQ7 VALID tAVEH tAVEL tAVWL tELEH tEHDX DATA INPUT |
Similar Part No. - M48Z128_10 |
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Similar Description - M48Z128_10 |
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