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M48T128Y-80PM1 Datasheet(PDF) 8 Page - STMicroelectronics |
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M48T128Y-80PM1 Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 23 page Operation modes M48T128Y, M48T128V 8/23 Doc ID 5746 Rev 6 2.1 READ mode The M48T128Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip enable) is low. The unique address specified by the 17 address inputs defines which one of the 131,072 bytes of data is to be accessed. Valid data will be available at the data I/O pins within tAVQV (address access time) after the last address input signal is stable, providing the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the chip enable access times (tELQV) or output enable access time (tGLQV). The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the address inputs are changed while E and G remain active, output data will remain valid for tAXQX (output data hold time) but will go indeterminate until the next address access. Figure 4. READ mode AC waveforms Note: WE = High. Table 3. READ mode AC characteristics Symbol Parameter(1) 1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). M48T128Y M48T128V Unit –70 –85 Min Max Min Max tAVAV READ cycle time 70 85 ns tAVQV Address valid to output valid 70 85 ns tELQV Chip enable low to output valid 70 85 ns tGLQV Output enable low to output valid 40 55 ns tELQX (2) 2. CL = 5 pF. Chip enable low to output transition 5 5 ns tGLQX (2) Output enable low to output transition 5 5 ns tEHQZ (2) Chip enable high to output Hi-Z 25 30 ns tGHQZ (2) Output enable high to output Hi-Z 25 30 ns tAXQX Address transition to output transition 10 5 ns AI01197 tAVAV tAVQV tAXQX tELQV tELQX tEHQZ tGLQV tGLQX tGHQZ DATA OUT A0-A16 E G DQ0-DQ7 VALID |
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