Operation modes

M48T128Y, M48T128V

8/23

Doc ID 5746 Rev 6

2.1

READ mode

The M48T128Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip

enable) is low. The unique address specified by the 17 address inputs defines which one of

the 131,072 bytes of data is to be accessed.

last address input signal is stable, providing the E and G access times are also satisfied. If

the E and G access times are not met, valid data will be available after the latter of the chip

three-state data I/O signals is controlled by E and G. If the outputs are activated before

data hold time) but will go indeterminate until the next address access.

Figure 4.

READ mode AC waveforms

Note:

WE = High.

Table 3.

READ mode AC characteristics

Symbol

1.

M48T128Y

M48T128V

Unit

–70

–85

Min

Max

Min

Max

READ cycle time

70

85

ns

Address valid to output valid

70

85

ns

Chip enable low to output valid

70

85

ns

Output enable low to output valid

40

55

ns

(2)

2.

Chip enable low to output transition

5

5

ns

(2)

Output enable low to output transition

5

5

ns

tEHQZ

(2)

Chip enable high to output Hi-Z

25

30

ns

(2)

Output enable high to output Hi-Z

25

30

ns

Address transition to output transition

10

5

ns

AI01197

tAVAV

tAVQV

tAXQX

tELQV

tELQX

tEHQZ

tGLQV

tGLQX

tGHQZ

DATA OUT

A0-A16

E

G

DQ0-DQ7

VALID