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74HC237 Datasheet(PDF) 9 Page - NXP Semiconductors |
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74HC237 Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 17 page 74HC237 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 10 January 2011 9 of 17 NXP Semiconductors 74HC237 3-to-8 line decoder, demultiplexer with address latches Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 10. Test circuit for measuring switching times 001aah768 tW tW tr tr tf VM VI negative pulse GND VI positive pulse GND 10 % 90 % 90 % 10 % VM VM VM tf VCC DUT RT VI VO CL G Table 9. Test data Type Input Load Test VI tr, tf CL 74HC237 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL |
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