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UBA2071T Datasheet(PDF) 9 Page - NXP Semiconductors |
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UBA2071T Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 35 page UBA2071_A_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 23 June 2008 9 of 35 NXP Semiconductors UBA2071; UBA2071A Half bridge control IC for CCFL backlighting 8.5 Non-overlap During each transition between the two states GL high/GH low and GL low/GH high, GL and GH will both be low for a fixed time tno (non-overlap time) to allow the half bridge point to be charged or discharged by the load current (presuming the load always has an inductive behavior), and thus enabling zero voltage switching, see Figure 5. 8.6 Low-side and high-side drivers The low-side and high-side drivers are identical. The output of each driver is connected to the equivalent gate of an external power MOSFET. The high-side driver is supplied by the bootstrap capacitor, which is charged from the VDD voltage via an internal diode when the low-side power MOSFETs is on. The low-side driver is directly supplied by the VDD voltage. 8.7 DC blocking capacitor charging When the IC is off, either because VVDD is too low, it is disabled via the EN pin, or it stopped after the time-out period during a fault condition, the low-side power switch (QLS in Figure 3) is turned on by making GL high. This ensures that the supply buffer capacitor of the floating supply (CFS in Figure 3) is fully charged at start-up. As a side effect the DC blocking capacitor (Cblock in Figure 3) will be completely discharged at start-up. To prevent large inrush currents during the first switching cycles the UBA2071 and UBA2071A can first charge the DC blocking capacitor at start-up. Fig 5. Oscillator, driver and half bridge voltages t VCF VCFH 0 t VGH − VSH VDD 0 t VGL VDD 0 t VHB VHV 0 tno 014aaa102 |
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