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TLE7279-2EV50 Datasheet(PDF) 7 Page - Infineon Technologies AG

Part # TLE7279-2EV50
Description  Low Dropout Voltage Regulator
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

TLE7279-2EV50 Datasheet(HTML) 7 Page - Infineon Technologies AG

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Data Sheet
7
Rev. 1.2, 2008-05-08
TLE7279-2
General Product Characteristics
4.2
Functional Range
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Thermal Resistance
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Max.
4.2.1
Input voltage
V
I
5.5
45
V
TLE7279-2GV50,
TLE7279-2EV50
4.2.2
4.2
45
V
TLE7279-2GV33
4.2.3
4.5
45
V
TLE7279-2GV26
4.2.4
Output capacitor’s requirements for
Stability
C
Q
470
nF
1)
1) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%
ESR(C
Q)
–3
2)
2) relevant ESR value at
f =10kHz
4.2.5
Junction temperature
T
j
-40
150
°C–
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
Package PG-DSO-14
4.3.1
Junction to Soldering Point1)
1) not subject to production test, specified by design
R
thJSP
30
K/W
measured to group
of pins 3, 4, 5, 10,
11, 12
4.3.2
Junction to Ambient1)
R
thJA
–53
K/W
2)
2) Specified
R
thJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
4.3.3
105
K/W
footprint only3)
3) Specified
R
thJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2
× 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).
4.3.4
74
K/W
300 mm2 heatsink
area on PCB3)
4.3.5
65
K/W
600 mm2 heatsink
area on PCB3)
Package PG-SSOP-14 Exposed Pad
4.3.6
Junction to Case1)
R
thJC
14
K/W
measured to
exposed pad
4.3.7
Junction to Ambient1)
R
thJA
–47
K/W
4.3.8
141
K/W
footprint only3)
4.3.9
66
K/W
300 mm2 heatsink
area on PCB3)
4.3.10
56
K/W
600 mm2 heatsink
area on PCB3)


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