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D2-24044-MR-T Datasheet(PDF) 11 Page - Intersil Corporation |
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D2-24044-MR-T Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 20 page  11 FN7678.0 September 3, 2010 Input and Control Functions PWM Inputs Eight PWM input pins provide the PWM inputs to the amplifier’s output stages. The PWM input pins are electrically single-ended, referenced to the PWMVDD and PWMGND supplies. PWM drive to the output stages is provided differentially on-chip, with the PWM input channels mapped to each of the high-side output FETs and the low-side output FETs that implement the individual power stages. Routing and assignment of the PWM input pins to the output FETS is defined by the configuration mode. Figures 11, 12, 13, and 14 show the mapping of these input pins to the outputs for each of the four configuration modes. All eight input pins however are not always used in each of the configuration modes. For example, in mode “00”, providing 3-level drive of two channels of full bridge outputs, or in mode “11” providing four independent half-bridge outputs, one PWM input is dedicated to each of the FETs. But in mode “01” that implements two 2-quadrant full-bridge outputs, only four PWM inputs are used, and the logical high/low states are routed to the FETs as needed. nPDN Input Pin The nPDN pin is a control input that is used to set the inactive (powered down) state, and also mute the outputs. It operates by turning off drive and internal sources to the PWM outputs, as well as turning off the PWM drive to those outputs. When an overcurrent condition is detected on an output, causing its overcurrent protection to latch and turn off that output, asserting the nPDN input resets the device, and clears this overcurrent state. The nPDN pin is active low, and inactive when at logic high level. nERRORA-D Output Pins Each of the four outputs includes an overload and overcurrent monitor. An overcurrent or overload condition asserts the nERROR output for that channel. These outputs are active low, open drain. Depending on the output mode configuration and need to monitor more than one output, these nERROR pins can be wire-or connected together. nOVRT Output Pin The nOVRT pin is an output that provides warning of a high temperature condition. It is an open drain, active low output. This pin provides only indication of high temperature. IREF Pin The IREF pin is used to control the overcurrent monitoring threshold. A 100kΩ resistor connects from this pin to ground. OCFG0, OCFG1 Input Pins These two pins are used to define the configuration of the four output stages. They are connected to logic high (PWMVDD) or logic ground (PWMGND) to set their level. Refer to “Output Mode Configurations” on page 14 for additional reference and definition. Protection The D2-24044 device includes monitors for protection of the system as well as the device itself. Certain levels of protection are managed on-chip, as shown in Figure 10. Other protection is integrated at the system level through the system controller, and involves system design decisions based on: • A short circuit, over-temperature, or undervoltage event will shut down the outputs. • Other operation depends on the PWM/system controller to properly manage full system protection operation. • Power supply sensors shut down the device if supply voltages drop below their design thresholds. • Overload and overcurrent monitors provide dual threshold status of high current conditions, providing both indication, and device shutdown if needed. • Chip temperature monitoring provides dual threshold status of high temperature conditions, providing both indication, and device shutdown if needed. Short-Circuit and Overcurrent Sensing Each PWM output FET includes a dual-threshold overcurrent sensor. Multiple functions occur depending on detection of overcurrent conditions: • The lower threshold is used to monitor fault conditions after the output stage filter inductor, such as shorts or overloads on the loudspeaker outputs. • The higher threshold monitors fault conditions of the PWM output pin. • The nERROR output asserts for the channel detecting the fault. • For the lower level threshold, nERROR remains asserted only through the duration of the overcurrent event. • For the higher level threshold, the output is shut down, and its nERROR output is asserted, and these remain latched until the controller acknowledges the fault event by turning off the channel’s PWM drive. (When the output is shutdown, its PWM output pin floats.) D2-24044 |
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