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ISL6265 Datasheet(PDF) 14 Page - Intersil Corporation |
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ISL6265 Datasheet(HTML) 14 Page - Intersil Corporation |
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14 / 24 page  14 FN6599.1 May 13, 2009 SVI WIRE Protocol The SVI wire protocol is based on the I2C bus concept. Two wires (serial clock (SVC) and serial data (SVD)), carry information between the AMD processor (master) and VR controller (slave) on the bus. The master initiates and terminates SVI transactions and drives the clock, SVC, during a transaction. The AMD processor is always the master and the voltage regulators are the slaves. The slave receives the SVI transactions and acts accordingly. Mobile SVI wire protocol timing is based on high-speed mode I2C. See AMD Griffin (Family 11h) processor publications for additional details. TABLE 3. SERIAL VID CODES SVID[6:0] VOLTAGE (V) SVID[6:0] VOLTAGE (V) SVID[6:0] VOLTAGE (V) SVID[6:0] VOLTAGE (V) 000_0000b 1.5500 010_0000b 1.1500 100_0000b 0.7500 110_0000b 0.3500 * 000_0001b 1.5375 010_0001b 1.1375 100_0001b 0.7375 110_0001b 0.3375 * 000_0010b 1.5250 010_0010b 1.1250 100_0010b 0.7250 110_0010b 0.3250 * 000_0011b 1.5125 010_0011b 1.1125 100_0011b 0.7125 110_0011b 0.3125 * 000_0100b 1.5000 010_0100b 1.1000 100_0100b 0.7000 110_0100b 0.3000 * 000_0101b 1.4875 010_0101b 1.0875 100_0101b 0.6875 110_0101b 0.2875 * 000_0110b 1.4750 010_0110b 1.0750 100_0110b 0.6750 110_0110b 0.2750 * 000_0111b 1.4625 010_0111b 1.0625 100_0111b 0.6625 110_0111b 0.2625 * 000_1000b 1.4500 010_1000b 1.0500 100_1000b 0.6500 110_1000b 0.2500 * 000_1001b 1.4375 010_1001b 1.0375 100_1001b 0.6375 110_1001b 0.2375 * 000_1010b 1.4250 010_1010b 1.0250 100_1010b 0.6250 110_1010b 0.2250 * 000_1011b 1.4125 010_1011b 1.0125 100_1011b 0.6125 110_1011b 0.2125 * 000_1100b 1.4000 010_1100b 1.0000 100_1100b 0.6000 110_1100b 0.2000 * 000_1101b 1.3875 010_1101b 0.9875 100_1101b 0.5875 110_1101b 0.1875 * 000_1110b 1.3750 010_1110b 0.9750 100_1110b 0.5750 110_1110b 0.1750 * 000_1111b 1.3625 010_1111b 0.9625 100_1111b 0.5625 110_1111b 0.1625 * 001_0000b 1.3500 011_0000b 0.9500 101_0000b 0.5500 111_0000b 0.1500 * 001_0001b 1.3375 011_0001b 0.9375 101_0001b 0.5375 111_0001b 0.1375 * 001_0010b 1.3250 011_0010b 0.9250 101_0010b 0.5250 111_0010b 0.1250 * 001_0011b 1.3125 011_0011b 0.9125 101_0011b 0.5125 111_0011b 0.1125 * 001_0100b 1.3000 011_0100b 0.9000 101_0100b 0.5000 111_0100b 0.1000 * 001_0101b 1.2875 011_0101b 0.8875 101_0101b 0.4875 * 111_0101b 0.0875 * 001_0110b 1.2750 011_0110b 0.8750 101_0110b 0.4750 * 111_0110b 0.0750 * 001_0111b 1.2625 011_0111b 0.8625 101_0111b 0.4625 * 111_0111b 0.0625 * 001_1000b 1.2500 011_1000b 0.8500 101_1000b 0.4500 * 111_1000b 0.0500 * 001_1001b 1.2375 011_1001b 0.8375 101_1001b 0.4375 * 111_1001b 0.0375 * 001_1010b 1.2250 011_1010b 0.8250 101_1010b 0.4250 * 111_1010b 0.0250 * 001_1011b 1.2125 011_1011b 0.8125 101_1011b 0.4125 * 111_1011b 0.0125 * 001_1100b 1.2000 011_1100b 0.8000 101_1100b 0.4000 * 111_1100b OFF 001_1101b 1.1875 011_1101b 0.7875 101_1101b 0.3875 * 111_1101b OFF 001_1110b 1.1750 011_1110b 0.7750 101_1110b 0.3750 * 111_1110b OFF 001_1111b 1.1625 011_1111b 0.7625 101_1111b 0.3625 * 111_1111b OFF NOTE: *Indicates a VID not required for AMD Family 10h processors. ISL6265 |
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