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SAK-TC1797-512F180E Datasheet(PDF) 8 Page - Infineon Technologies AG |
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SAK-TC1797-512F180E Datasheet(HTML) 8 Page - Infineon Technologies AG |
8 / 190 page TC1797 Summary of Features Data Sheet 4 V1.1, 2009-04 1 Summary of Features • High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Single precision Floating Point Unit (FPU) – 180 or 150 1) MHz operation at full temperature range • 32-bit Peripheral Control Processor with single cycle instruction (PCP2) – 16 Kbyte Parameter Memory (PRAM) – 32 Kbyte Code Memory (CMEM) – 180 or150 1) MHz operation at full temperature range • Multiple on-chip memories –4 or 3 1) Mbyte Program Flash Memory (PFLASH) with ECC – 64 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation – 128 Kbyte Data Memory (LDRAM) – 40 Kbyte Code Scratchpad Memory (SPRAM) – Instruction Cache: up to 16 Kbyte (ICACHE, configurable) – Data Cache: up to 4 Kbyte (DCACHE, configurable) – 8 Kbyte Overlay Memory (OVRAM) – 16 Kbyte BootROM (BROM) • 16-Channel DMA Controller • 32-bit External Bus Interface Unit (EBU) with – 32-bit demultiplexed / 16-bit multiplexed external bus interface (3.3V, 2.5V) – Support for Burst Flash memory devices – Scalable external bus timing up to 75 MHz • Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels serviced by CPU or PCP2 • High performing on-chip bus structure – 64-bit Local Memory Buses between CPU, EBU, Flash and Data Memory – 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units – One bus bridges (LFI Bridge) • Versatile On-chip Peripheral Units – Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection – Two High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction – Two serial Micro Second Bus interface (MSC) for serial port expansion to external power devices 1) Derivative dependent. |
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