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ADSP-BF526 Datasheet(PDF) 10 Page - Analog Devices |
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ADSP-BF526 Datasheet(HTML) 10 Page - Analog Devices |
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10 / 80 page  Rev. PrG | Page 10 of 80 | February 2009 ADSP-BF522/523/524/525/526/527 Preliminary Technical Data REAL-TIME CLOCK The real-time clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz crystal external to the Blackfin processor. The RTC peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a low-power state. The RTC provides several programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a pro- grammed alarm time. The 32.768 kHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60-second counter, a 60-minute counter, a 24-hour counter, and an 32,768-day counter. When enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. There are two alarms: The first alarm is for a time of day. The second alarm is for a day and time of that day. The stopwatch function counts down from a programmed value, with one-second resolution. When the stopwatch is enabled and the counter underflows, an interrupt is generated. Like the other peripherals, the RTC can wake up the processor from sleep mode upon generation of any RTC wakeup event. Additionally, an RTC wakeup event can wake up the processor from deep sleep mode or cause a transition from the hibernate state. Connect RTC pins RTXI and RTXO with external components as shown in Figure 4. WATCHDOG TIMER The processor includes a 32-bit timer that can be used to imple- ment a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state through generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software. The programmer initial- izes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the pro- grammed value. This protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. If configured to generate a hardware reset, the watchdog timer resets both the core and the processor peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register. The timer is clocked by the system clock (SCLK), at a maximum frequency of fSCLK. TIMERS There are nine general-purpose programmable timer units in the processors. Eight timers have an external pin that can be configured either as a pulse width modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an external clock input to the sev- eral other associated PF pins, an external clock input to the PPI_CLK input pin, or to the internal SCLK. The timer units can be used in conjunction with the two UARTs to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. The timers can generate interrupts to the processor core provid- ing periodic events for synchronization, either to the system clock or to a count of external signals. In addition to the eight general-purpose programmable timers, a ninth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts. UP/DOWN COUNTER AND THUMBWHEEL INTERFACE A 32-bit up/down counter is provided that can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or manual thumb wheels. The counter can also operate in general-purpose up/down count modes. Then, count direction is either controlled by a level-sensitive input pin or by two edge detectors. A third input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumb wheels. All three pins have a programmable debouncing circuit. An internal signal forwarded to the timer unit enables one timer to measure the intervals between count events. Boundary regis- ters enable auto-zero operation or simple system warning by interrupts when programmable count values are exceeded. Figure 4. External Components for RTC RTXO C1 C2 X1 SUGGESTED COMPONENTS: X1 = ECL IPTEK EC38J (THROUGH-HOLE PACKAGE) OR EPSO N MC40512pF LOAD (SURFACE-MO UNT PACKAGE) C1 = 22 pF C2 = 22 pF R1 = 10 M Ω NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECI FIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2 SPECI FI CATIO NS ASSUME BOARD TRACE CAPACITANCE OF 3 pF. RTXI R1 |
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