 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADSP-BF518 Datasheet(PDF) 5 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
ADSP-BF518 Datasheet(HTML) 5 Page - Analog Devices |
|
|
5 / 62 page  ADSP-BF512/BF514/BF516/BF518(F) Preliminary Technical Data Rev. PrE | Page 5 of 62 | March 2009 Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The memory manage- ment unit (MMU) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. The Blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instruc- tions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support a limited multi-issue capability, where a 32-bit instruc- tion can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle. The Blackfin processor assembly language uses an algebraic syn- tax for ease of coding and readability. The architecture has been optimized for use in conjunction with the C/C++ compiler, resulting in fast and efficient software implementations. MEMORY ARCHITECTURE The ADSP-BF512/BF514/BF516/BF518(F) processors view memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low-latency on-chip memory as cache or SRAM, and larger, lower-cost and performance off-chip memory systems. See Figure 2. The on-chip L1 memory system is the highest-performance memory available to the Blackfin processor. The off-chip mem- ory system, accessed through the external bus interface unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing up to 132M bytes of physical memory. The memory DMA controller provides high-bandwidth data- movement capability. It can perform block transfers of code or data between the internal memory and the external memory spaces. Internal (On-Chip) Memory The ADSP-BF512/BF514/BF516/BF518(F) processors have three blocks of on-chip memory providing high-bandwidth access to the core. The first block is the L1 instruction memory, consisting of 48K bytes SRAM, of which 16K bytes can be configured as a four-way set-associative cache. This memory is accessed at full processor speed. The second on-chip memory block is the L1 data memory, con- sisting of up to two banks of up to 32K bytes each. Each memory bank is configurable, offering both cache and SRAM functional- ity. This memory block is accessed at full processor speed. The third memory block is a 4K byte scratchpad SRAM which runs at the same speed as the L1 memories, but is only accessible as data SRAM and cannot be configured as cache memory. External (Off-Chip) Memory External memory is accessed via the EBIU. This 16-bit interface provides a glueless connection to a bank of synchronous DRAM (SDRAM) as well as up to four banks of asynchronous memory devices including flash, EPROM, ROM, SRAM, and memory mapped I/O devices. The SDRAM controller can be programmed to interface to up to 128M bytes of SDRAM. A separate row can be open for each SDRAM internal bank and the SDRAM controller supports up to four internal SDRAM banks, improving overall performance. Figure 2. ADSP-BF512/BF514/BF516/BF518(F) Internal/External Memory Map RESERVED CORE MMR REGISTERS (2M BYTES) RESERVED SCRATCHPAD SRAM (4K BYTES) INSTRUCTION BANK B SRAM (16K BYTES) SYSTEM MMR REGISTERS (2M BYTES) RESERVED RESERVED DATA BANK B SRAM / CACHE (16K BYTES) DATA BANK B SRAM (16K BYTES) DATA BANK A SRAM / CACHE (16K BYTES) ASYNC MEMORY BANK 3 (1M BYTES) ASYNC MEMORY BANK 2 (1M BYTES) ASYNC MEMORY BANK 1 (1M BYTES) ASYNC MEMORY BANK 0 (1M BYTES) SDRAM MEMORY (16M BYTES - 128MBYTES) INSTRUCTION BANK C SRAM/CACHE (16K BYTES) 0xFFFF FFFF 0xFFE0 0000 0xFFB0 0000 0xFFA1 4000 0xFFA1 0000 0xFF90 8000 0xFF90 4000 0xFF80 8000 0xFF804000 0x2040 0000 0x20300000 0x2020 0000 0x2010 0000 0x2000 0000 0xEF00 0000 0x0000 0000 0xFFC0 0000 0xFFB0 1000 0xFFA0 0000 DATA BANK A SRAM (16K BYTES) 0xFF90 0000 0xFF800000 RESERVED RESERVED 0xFFA0 8000 INSTRUCTIONBANKA SRAM (16K BYTES) RESERVED BOOT ROM (32K BYTES) 0xEF00 8000 RESERVED 0x08 00 0000 0xFFA0 4000 |
Similar Part No. - ADSP-BF518 |
|
Similar Description - ADSP-BF518 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
