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ADSP-21465W Datasheet(PDF) 7 Page - Analog Devices |
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ADSP-21465W Datasheet(HTML) 7 Page - Analog Devices |
7 / 60 page ADSP-21462W/ADSP-21465W/ADSP-21467 Preliminary Technical Data Rev. PrA | Page 7 of 60 | November 2008 External Memory Execution In the ADSP-21462W/ADSP-21465W/ADSP-21467, the pro- gram sequencer can execute code directly from external memory bank 0 (SRAM, as well as DDR2 DRAM). This allows more options to a user in terms of code and data storage. With external execution, programs run at slower speeds since 48-bit instructions are fetched in parts from a 16-bit external bus cou- pled with the inherent latency of fetching instructions from DDR2 DRAM. VISA mode and SIMD mode accesses are sup- ported for DDR2 space. However, external memory execution from DDR2 space is different for VISA and non-VISA mode. DDR2 Support The ADSP-21462W/ADSP-21465W/ADSP-21467 supports a 16-bit DDR2 interface operating at a maximum frequency of half the core clock. Execution from external memory is sup- ported. External memory devices up to 2 Gbits in size can be supported. Delay line DMA functionality supported. DDR2 DRAM Controller The DDR2 DRAM controller provides an 16-bit interface to up to four separate banks of industry-standard DDR2 DRAM devices. Fully compliant with the DDR2 DRAM standard, each bank can has its own memory select line (DDR2_CS3- DDR2_CS0), and can be configured to contain between 32M bytes and 256M bytes of memory. DDR2 DRAM external mem- ory address space is shown in Table 5 A set of programmable timing parameters is available to config- ure the DDR2 DRAM banks to support memory devices. Table 3. ADSP-21462W/ADSP-21465W/ADSP-21467 Internal Memory Space IOP Registers 0x0000 0000–0x0003 FFFF Long Word (64 bits) Extended Precision Normal or Instruction Word (48 bits) Normal Word (32 bits) Short Word (16 bits) BLOCK 0 ROM 0x0004 0000–0x0004 7FFF BLOCK 0 ROM 0x0008 0000–0x0008 AAA9 BLOCK 0 ROM 0x0008 0000–0x0008 FFFF BLOCK 0 ROM 0x0010 0000–0x0011 FFFF Reserved 0x0004 8000–0x0004 8FFF Reserved 0x0009 0000–0x0009 1FFF Reserved 0x0009 0000–0x0009 1FFF Reserved 0x0012 0000–0x0012 3FFF BLOCK 0 RAM 0x0004 9000–0x0004 EFFF BLOCK 0 RAM 0x0008 C000-0x0009 3FFF BLOCK 0 RAM 0x0009 2000-0x0009 DFFF BLOCK 0 RAM 0x0012 4000–0x0013 BFFF Reserved 0x0004 F000–0x0004 FFFF Reserved 0x0009 E000–0x0009 FFFF Reserved 0x0009 E000–0x0009 FFFF Reserved 0x0013 C000–0x0013 FFFF BLOCK 1 ROM 0x0005 0000–0x0005 7FFF BLOCK 1 ROM 0x000A 0000–0x000A AAA9 BLOCK 1 ROM 0x000A 0000–0x000A FFFF BLOCK 1 ROM 0x0014 0000-0x0015 FFFF Reserved 0x0005 8000–0x0005 8FFF Reserved 0x000B 000–0x000B 1FFF Reserved 0x000B 0000–0x000B 1FFF Reserved 0x0016 0000-0x0016 3FFF BLOCK 1 RAM 0x0005 9000–0x0005 EFFF BLOCK 1 RAM 0x000A C000-0x000B 3FFF BLOCK 1 RAM 0x000B 2000-0x000B DFFF BLOCK 1 RAM 0x0016 4000-0x0017 BFFF Reserved 0x0005 F000–0x0005 FFFF Reserved 0x000B E000–0x000B FFFF Reserved 0x000B E000–0x000B FFFF Reserved 0x0017 C000–0x0017 FFFF BLOCK 2 RAM 0x0006 0000–0x0006 3FFF BLOCK 2 RAM 0x000C 0000–0x000C 5554 BLOCK 2 RAM 0x000C 0000-0x000C 7FFF BLOCK 2 RAM 0x0018 0000–0x0018 FFFF Reserved 0x0006 4000–0x0006 FFFF Reserved 0x000C 8000–0x000D FFFF Reserved 0x000C 8000–0x000D FFFF Reserved 0x0019 0000–0x001B FFFF BLOCK 3 RAM 0x0007 0000–0x0007 3FFF BLOCK 3 RAM 0x000E 0000–0x000E 5554 BLOCK 3 RAM 0x000E 0000–0x000E 7FFF BLOCK 3 RAM 0x001C 0000–0x001C FFFF Reserved 0x0007 4000–0x0007 FFFF Reserved 0x000E 8000–0x000F FFFF Reserved 0x000E 8000–0x000F FFFF Reserved 0x001D 0000–0x001F FFFF |
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