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PCKEL14D Datasheet(PDF) 8 Page - NXP Semiconductors

Part # PCKEL14D
Description  2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCKEL14D Datasheet(HTML) 8 Page - NXP Semiconductors

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Philips Semiconductors
PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
Product data
Rev. 01 — 14 October 2002
8 of 15
9397 750 09564
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
9.
Dynamic characteristics
[1]
VEE can vary ±0.3 V.
[2]
Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW transitions.
[3]
Vi(p-p)(min) is minimum input swing for which AC parameters are guaranteed.
Table 8:
AC characteristics
(VCC = 2.375 V to 3.8 V; VEE = 0 V) or (VCC =0V; VEE = −2.375 V to −3.8 V) [1]
Symbol
Parameter
Conditions
Tamb = −40 °C
Tamb = +25 °C
Tamb = +85 °C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fmax
maximum toggle
frequency
see Figure 4
-
> 1-
-
> 1-
-
> 1-
GHz
tPLH
LOW-to-HIGH
propagation delay
CLK to Q (diff);
3.3 V
400
-
720
450
-
780
475
-
830
ps
CLK to Q (diff);
2.5 V
400
-
800
450
-
940
500
-
970
ps
tPHL
HIGH-to-LOW
propagation delay
CLK to Q (SE)
330
-
770
350
680
830
370
-
880
ps
SCLK to Q
330
-
770
350
680
830
370
-
880
ps
tSKEW
skew time
part-to-part
-
-
200
-
-
200
-
-
200
ps
within-device;
3.3 V
[2]
-
-
50
-
-
50
-
-
50
ps
within-device;
2.5 V
[2]
-
-
70
-
-
70
-
-
70
ps
tJITTER
cycle-to cycle jitter
-
0.2
< 1
-
0.2
< 1
-
0.2
< 1
ps
tsu
EN set-up time
0
-
-
0
-
-
0
-
-
ps
th
EN hold time
0
-
-
0
-
-
0
-
-
ps
Vi(p-p)
input swing CLK
[3]
150
-
1000
150
-
1000
150
-
1000 mV
tr/tf
output rise/fall times
Q pins
(20% - 80%);
3.3 V
230
-
500
230
-
500
230
-
500
ps
Q pins
(20% - 80%);
2.5 V
230
-
600
230
-
600
230
-
625
ps


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