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MSC8102M4000 Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc |
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MSC8102M4000 Datasheet(HTML) 6 Page - Freescale Semiconductor, Inc |
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6 / 80 page  MSC8102, Rev. 12 vi Freescale Semiconductor Table 4. DMA Controller Feature Description Multi-Channel DMA Controller • 16 time-multiplexed unidirectional channels. • Services up to four external peripherals. • Supports DONE or DRACK protocol on two external peripherals. • Each channel group services 16 internal requests generated by eight internal FIFOs. Each FIFO generates: • a watermark request to indicate that the FIFO contains data for the DMA to empty and write to the destination • a hungry request to indicate that the FIFO can accept more data. • Priority-based time-multiplexing between channels using 16 internal priority levels • A flexible channel configuration: • All channels support all features. • All channels connect to the 60x-compatible system bus or local bus. • Flyby transfers in which a single data access is transferred directly from the source to the destination without using a DMA FIFO. Table 5. Serial Interfaces Feature Description Time-Division Multiplexing (TDM) Up to four independent TDM modules, each with the following features: • Either totally independent receive and transmit, each having one data line, one clock line, and one frame sync line or four data lines, one clock and one frame sync that are shared between the transmit and receive. • Glueless interface to E1/T1 framers and MVIP, SCAS, and H.110 buses. • Hardware A-law/ µ-law conversion • Up to 50 Mbps per TDM (50 MHz bit clock if one data line is used, 25 MHz if two data lines are used, 12.5 MHz if four data lines are used). • Up to 256 channels. • Up to 16 MB per channel buffer (granularity 8 bytes), where A/ µ law buffer size is double (granularity 16 byte) • Receive buffers share one global write offset pointer that is written to the same offset relative to their start address. • Transmit buffers share one global read offset pointer that is read from the same offset relative to their start address. • All channels share the same word size. • Two programmable receive and two programmable transmit threshold levels with interrupt generation that can be used, for example, to implement double buffering. • Each channel can be programmed to be active or inactive. • 2-, 4-, 8-, or 16-bit channels are stored in the internal memory as 2-, 4-, 8-, or 16-bit channels, respectively. • The TDM transmitter sync signal (TxTSYN) can be configured as either input or output. • Frame sync and data signals can be programmed to be sampled either on the rising edge or on the falling edge of the clock. • Frame sync can be programmed as active low or active high. • Selectable delay (0–3 bits) between the Frame Sync signal and the beginning of the frame. • MSB or LSB first support. |
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