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MSC8102RM Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc |
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MSC8102RM Datasheet(HTML) 7 Page - Freescale Semiconductor, Inc |
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7 / 80 page  MSC8102, Rev. 12 Freescale Semiconductor vii UART • Two signals for transmit data and receive data. • No clock, asynchronous mode. • Can be serviced either by the SC140 DSP cores or an external host on the 60x-compatible system bus or on the DSI. • Full-duplex operation. • Standard mark/space non-return-to-zero (NRZ) format. • 13-bit baud rate selection. • Programmable 8-bit or 9-bit data format. • Separately enabled transmitter and receiver. • Programmable transmitter output polarity. • Two receiver walk-up methods: • Idle line walk-up. • Address mark walk-up. • Separate receiver and transmitter interrupt requests. • Eight flags, the first five can generate interrupt request: • Transmitter empty. • Transmission complete. • Receiver full. • Idle receiver input. • Receiver overrun. • Noise error. • Framing error. • Parity error. • Receiver framing error detection. • Hardware parity checking. • 1/16 bit-time noise detection. • Maximum bit rate 6.25 Mbps. • Single-wire and loop operations. General-Purpose I/O (GPIO) port • 32 bidirectional signal lines that either serve the peripherals or act as programmable I/O ports. • Each port can be programmed separately to serve up to two dedicated peripherals, and each port supports open-drain output mode. Table 6. Miscellaneous Modules Feature Description Timers Two modules of 16 timers each. Each timer has the following features: • Cyclic or one-shot. • Input clock polarity control. • Interrupt request when counting reaches a programmed threshold. • Pulse or level interrupts. • Dynamically updated programmed threshold. • Read counter any time. Watchdog mode for the timers that connect to the device. Hardware Semaphores Eight coded hardware semaphores, locked by simple write access without need for read-modify-write mechanism. Global Interrupt Controller (GIC) • Consolidation of chip maskable interrupt and non-maskable interrupt sources and routing to INT_OUT, NMI_OUT, and to the cores. • Generation of 32 virtual interrupts (eight to each SC140 core) by a simple write access. • Generation of virtual NMI (one to each SC140 core) by a simple write access. Table 5. Serial Interfaces Feature Description |
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