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58 page 
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 58 Freescale Semiconductor I 2C Figure 34. I2C AC Test Load Figure 35. I2C Bus AC Timing Diagram Capacitive load for each bus line Cb —400 pF Note: 1.The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I 2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I 2C timing (I2) for the time that the data with respect to the START condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I 2C timing (I2) for the time that the data with respect to the STOP condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. 2. As a transmitter, the MPC8568 provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP condition. When the MPC8568 acts as the I2C bus master while transmitting, the MPC8568 drives both SCL and SDA. As long as the load on SCL and SDA are balanced, the MPC8568 would not cause unintended generation of START or STOP condition. Therefore, the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for the MPC8568 as transmitter, application note AN2919 referred to in note 4 below is recommended. 3. The maximum tI2DXKL has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal. 4.The requirements for I2C frequency calculation must be followed. Refer to Freescale application note AN2919, Determining the I2C Frequency Divider Ratio for SCL Table 47. I2C AC Electrical Specifications (continued) At recommended operating conditions with OVDD of 3.3V ± 5%. All values refer to VIH (min) and VIL (max) levels (see Table 46). Parameter Symbol 1 Min Max Unit Output Z0 = 50 Ω OVDD/2 RL = 50 Ω Sr S SDA SCL tI2SXKL tI2CL tI2CH tI2DXKL tI2DVKH tI2SXKL tI2SVKH tI2KHKL tI2PVKH PS |
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