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64 page 
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 64 Freescale Semiconductor Local Bus Controller (eLBC) Figure 35. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 8 or 16 (PLL Bypass Mode) tLBIXKL2 tLBIVKH1 Internal launch/capture clock UPM Mode Input Signal: LUPWAIT T1 T3 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] GPCM Mode Output Signals: LCS[0:7]/LWE T2 T4 Input Signals: LAD[0:31]/LDP[0:3] LCLK tLBKLOV1 tLBKLOZ1 tLBKLOX1 tLBIXKH1 GPCM Mode Input Signal: LGTA tLBIVKL2 |
