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51 page 
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 51 Local Bus Figure 27. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Bypass Mode) tLBIVKH1 tLBIXKL2 Internal launch/capture clock UPM Mode Input Signal: LUPWAIT T1 T3 Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] GPCM Mode Output Signals: LCS[0:7]/LWE tLBKLOV1 tLBKLOZ1 LCLK tLBKLOX1 tLBIXKH1 GPCM Mode Input Signal: LGTA tLBIVKL2 |
